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Message-Id: <20251030-nvidia-nand-v1-1-7614e1428292@gmail.com>
Date: Thu, 30 Oct 2025 18:47:25 +0000
From: Charan Pedumuru <charan.pedumuru@...il.com>
To: Miquel Raynal <miquel.raynal@...tlin.com>,
Richard Weinberger <richard@....at>, Vignesh Raghavendra <vigneshr@...com>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>, Stefan Agner <stefan@...er.ch>,
Lucas Stach <dev@...xeye.de>
Cc: linux-mtd@...ts.infradead.org, devicetree@...r.kernel.org,
linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org,
Charan Pedumuru <charan.pedumuru@...il.com>
Subject: [PATCH] dt-bindings: mtd: nvidia,tegra20-nand: convert to DT
schema
Convert NVIDIA Tegra NAND Flash Controller binding to YAML format.
Changes during Conversion:
- Define new properties `power-domains` and `operating-points-v2`
to resolve errors generated by `dtb_check`.
- Add the `#address-cells` and `#size-cells` properties to the parent
node to fix errors reported by `dt_check`, and include these properties
in the `required` section, as they are not mentioned in the text binding.
Signed-off-by: Charan Pedumuru <charan.pedumuru@...il.com>
---
.../bindings/mtd/nvidia,tegra20-nand.yaml | 157 +++++++++++++++++++++
.../bindings/mtd/nvidia-tegra20-nand.txt | 64 ---------
2 files changed, 157 insertions(+), 64 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml
new file mode 100644
index 000000000000..67b3c45566db
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml
@@ -0,0 +1,157 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/nvidia,tegra20-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra NAND Flash Controller
+
+maintainers:
+ - Jonathan Hunter <jonathanh@...dia.com>
+
+description:
+ Device tree bindings for the NVIDIA Tegra NAND Flash Controller (NFC).
+ The controller supports a single NAND chip with specific properties.
+
+properties:
+ compatible:
+ const: nvidia,tegra20-nand
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: nand
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: nand
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ power-domains:
+ maxItems: 1
+
+ operating-points-v2:
+ maxItems: 1
+
+patternProperties:
+ "^nand@[0-5]$":
+ type: object
+ description: Individual NAND chip connected to the NAND controller
+ properties:
+ reg:
+ maxItems: 1
+
+ nand-ecc-mode:
+ description:
+ Operation mode of the NAND ECC, currently only hardware
+ mode supported
+ const: hw
+
+ nand-ecc-algo:
+ description: Algorithm for NAND ECC when using hw ECC mode
+ enum:
+ - rs
+ - bch
+
+ nand-bus-width:
+ description: Width of the NAND flash bus in bits
+ enum: [8, 16]
+ default: 8
+
+ nand-on-flash-bbt:
+ description: Use an on-flash bad block table to track bad blocks
+ type: boolean
+
+ nand-ecc-maximize:
+ description:
+ Maximize ECC strength for the NAND chip, overriding
+ default strength selection
+ type: boolean
+
+ nand-ecc-strength:
+ description: Number of bits to correct per ECC step (512 bytes)
+ enum: [4, 6, 8, 14, 16]
+
+ nand-is-boot-medium:
+ description: Ensures ECC strengths are compatible with the boot ROM
+ type: boolean
+
+ wp-gpios:
+ description: GPIO specifier for the write protect pin
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+ patternProperties:
+ "^partition@[0-9a-f]+$":
+ $ref: /schemas/mtd/mtd.yaml#
+ description:
+ Optional MTD partitions for the NAND chip, as defined in mtd.yaml
+
+ required:
+ - reg
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - '#address-cells'
+ - '#size-cells'
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/tegra20-car.h>
+ #include <dt-bindings/gpio/tegra-gpio.h>
+
+ nand-controller@...08000 {
+ compatible = "nvidia,tegra20-nand";
+ reg = <0x70008000 0x100>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
+ clock-names = "nand";
+ resets = <&tegra_car 13>;
+ reset-names = "nand";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ nand-bus-width = <8>;
+ nand-on-flash-bbt;
+ nand-ecc-algo = "bch";
+ nand-ecc-strength = <8>;
+ wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
deleted file mode 100644
index 4a00ec2b2540..000000000000
--- a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
+++ /dev/null
@@ -1,64 +0,0 @@
-NVIDIA Tegra NAND Flash controller
-
-Required properties:
-- compatible: Must be one of:
- - "nvidia,tegra20-nand"
-- reg: MMIO address range
-- interrupts: interrupt output of the NFC controller
-- clocks: Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
- - nand
-- resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names: Must include the following entries:
- - nand
-
-Optional children nodes:
-Individual NAND chips are children of the NAND controller node. Currently
-only one NAND chip supported.
-
-Required children node properties:
-- reg: An integer ranging from 1 to 6 representing the CS line to use.
-
-Optional children node properties:
-- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
- "hw" is supported.
-- nand-ecc-algo: string, algorithm of NAND ECC.
- Supported values with "hw" ECC mode are: "rs", "bch".
-- nand-bus-width : See nand-controller.yaml
-- nand-on-flash-bbt: See nand-controller.yaml
-- nand-ecc-strength: integer representing the number of bits to correct
- per ECC step (always 512). Supported strength using HW ECC
- modes are:
- - RS: 4, 6, 8
- - BCH: 4, 8, 14, 16
-- nand-ecc-maximize: See nand-controller.yaml
-- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
- are chosen.
-- wp-gpios: GPIO specifier for the write protect pin.
-
-Optional child node of NAND chip nodes:
-Partitions: see mtd.yaml
-
- Example:
- nand-controller@...08000 {
- compatible = "nvidia,tegra20-nand";
- reg = <0x70008000 0x100>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
- clock-names = "nand";
- resets = <&tegra_car 13>;
- reset-names = "nand";
-
- nand@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- nand-bus-width = <8>;
- nand-on-flash-bbt;
- nand-ecc-algo = "bch";
- nand-ecc-strength = <8>;
- wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
- };
- };
---
base-commit: 43edce71d70c603d3f3f1b1c886f65cd02d80c24
change-id: 20251011-nvidia-nand-024cc7ae8b0a
Best regards,
--
Charan Pedumuru <charan.pedumuru@...il.com>
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