linux-kernel - Re: [PATCH v2 01/13] dt-bindings: serial: renesas,rsci: Document RZ/G3E support

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Message-ID: <20251030-regroup-garter-c70c7fc6a71a@spud>
Date: Thu, 30 Oct 2025 19:20:56 +0000
From: Conor Dooley <conor@...nel.org>
To: Biju <biju.das.au@...il.com>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	Jiri Slaby <jirislaby@...nel.org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Magnus Damm <magnus.damm@...il.com>,
	Biju Das <biju.das.jz@...renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
	linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org,
	devicetree@...r.kernel.org, linux-renesas-soc@...r.kernel.org
Subject: Re: [PATCH v2 01/13] dt-bindings: serial: renesas,rsci: Document
 RZ/G3E support

On Thu, Oct 30, 2025 at 05:57:49PM +0000, Biju wrote:
> From: Biju Das <biju.das.jz@...renesas.com>
> 
> Add documentation for the serial communication interface (RSCI) found on
> the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical
> to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared
> to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E
> has 6 clocks(5 module clocks + 1 external clock) compared to 3 clocks
> (2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets.
> 
> Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
> ---
> v1->v2:
>  * Updated commit message
>  * Added resets:false for non RZ/G3E SoCs.

Acked-by: Conor Dooley <conor.dooley@...rochip.com>
pw-bot: not-applicable

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