linux-kernel - [PATCH 2/3] arm64: dts: intel: Add Agilex5 SVC node with memory region

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Message-ID: <2ab538d19d8287517f608d5169c80944bc1eaf3a.1761648711.git.khairul.anuar.romli@altera.com>
Date: Thu, 30 Oct 2025 11:30:08 +0800
From: Khairul Anuar Romli <khairul.anuar.romli@...era.com>
To: Dinh Nguyen <dinguyen@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Mahesh Rao <mahesh.rao@...era.com>,
	linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org,
	Khairul Anuar Romli <khairul.anuar.romli@...era.com>
Subject: [PATCH 2/3] arm64: dts: intel: Add Agilex5 SVC node with memory region

Introduce the Stratix10 SoC Service Layer (SVC) node for Agilex5 SoCs. This
node includes the compatible string "intel,agilex5-svc" and references a
reserved memory region used for communication with the Secure Device
Manager (SDM).

Agilex5 introduces changes in how reserved memory is mapped and accessed
compared to previous SoC generations. This commit updates the device tree
structure to support Agilex5-specific handling of the SVC interface.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@...era.com>
---
Changes in v2:
	- Rephrase commit message to exclude mentioning iommu
	- Remove iommu property from svc node
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index a13ccee3c4c3..a003720b2995 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -841,5 +841,13 @@ queue7 {
 				};
 			};
 		};
+
+		firmware {
+			svc {
+				compatible = "intel,agilex5-svc";
+				method = "smc";
+				memory-region = <&service_reserved>;
+			};
+		};
 	};
 };
-- 
2.43.7