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Message-ID: <20251030060155.2342604-1-ryan_chen@aspeedtech.com>
Date: Thu, 30 Oct 2025 14:01:54 +0800
From: Ryan Chen <ryan_chen@...eedtech.com>
To: ryan_chen <ryan_chen@...eedtech.com>, Thomas Gleixner
<tglx@...utronix.de>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski
<krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Joel Stanley
<joel@....id.au>, Andrew Jeffery <andrew@...econstruct.com.au>,
<jk@...econstruct.com.au>, Kevin Chen <kevin_chen@...eedtech.com>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <linux-aspeed@...ts.ozlabs.org>
Subject: [PATCH v6 0/1] Update correct AST2700 interrupt controller binding
Update the AST2700 interrupt controller binding to match the actual
hardware and the irq-aspeed-intc driver behavior.
v6:
- aspeed,ast2700-intc.yaml
update interrupt-cells, interrupts.
v5:
- Adds two new YAML bindings:
- aspeed,ast2700-intc0.yaml
- aspeed,ast2700-intc1.yaml
- irq-aspeed-intc.c
- add aspeed,ast2700-intc0-ic, aspeed,ast2700-intc0-ic compatible.
v4:
- aspeed,ast2700-intc.yaml
- Clarify the relationship between INTC0/INTC1 parent nodes, the
aspeed,ast2700-intc-ic child nodes, and the GIC.
- Add a block diagram and DT examples showing the cascaded wiring
(GIC <- INTC0 <- INTC1 children).
- Mirrors the datasheet-described topology and register map, including
the separation of INTC0/INTC1 regions.
- Lets DT unambiguously express first-level (GIC parent) and cascaded
second-level (INTC0 parent) interrupt controllers via examples that
use `interrupts` for INTC0 children and `interrupts-extended` for
INTC1 children routed into INTC0.
- irq-ast2700-intc.c
- Drop all string decoding and human readable tables.
Debugfs now dumps raw routing/protection registers only.
- Split into a separate source file and made it modular
- If the compatible not match ast2700-intc0/1, bail out return -ENODEV.
v3:
- aspeed,ast2700-intc.yaml
- Clarify the relationship between INTC0/INTC1 parent nodes, the
aspeed,ast2700-intc-ic child nodes, and the GIC.
- Add a block diagram and DT examples showing the cascaded wiring
(GIC <- INTC0 <- INTC1 children).
- Mirrors the datasheet-described topology and register map, including
the separation of INTC0/INTC1 regions and their routing/protection
registers.
- Lets DT unambiguously express first-level (GIC parent) and cascaded
second-level (INTC0 parent) interrupt controllers via examples that
use `interrupts` for INTC0 children and `interrupts-extended` for
INTC1 children routed into INTC0.
- irq-aspeed-intc.c
- separate c file from irq-aspeed-intc.c
- make m
v2:
- fix dt bindingcheck
Ryan Chen (1):
dt-bindings: interrupt-controller: aspeed,ast2700: correct
#interrupt-cells and interrupts count
.../interrupt-controller/aspeed,ast2700-intc.yaml | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
--
2.34.1
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