linux-kernel - [PATCH v3 0/3] spi-cadence: support transmission with bits_per

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-Id: <20251031073003.3289573-1-jun.guo@cixtech.com>
Date: Fri, 31 Oct 2025 15:30:00 +0800
From: Jun Guo <jun.guo@...tech.com>
To: peter.chen@...tech.com,
	fugang.duan@...tech.com,
	robh@...nel.org,
	krzk+dt@...nel.org,
	conor+dt@...nel.org,
	broonie@...nel.org
Cc: linux-spi@...r.kernel.org,
	michal.simek@....com,
	cix-kernel-upstream@...tech.com,
	linux-arm-kernel@...ts.infradead.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	"jun.guo" <jun.guo@...tech.com>
Subject: [PATCH v3 0/3] spi-cadence: support transmission with bits_per_word of 16 and 32

From: "jun.guo" <jun.guo@...tech.com>

The Cadence SPI IP supports configurable FIFO data widths during
integration. On some SoCs, the FIFO data width is designed to be 16 or
32 bits at the chip design stage. However, the current driver only
supports communication with an 8-bit FIFO data width. Therefore, these
patches are added to enable the driver to support communication with
16-bit and 32-bit FIFO data widths.

This series introduces the following enhancements for Cadence SPI
controller support on arm64 platforms:

Patch 1: Add a compatible string "cix,sky1-spi-r1p6" for the cix
sky1 SoC.
Patch 2: Update DT binding docs to support cix sky1 SoC.
Patch 3: Enhance the SPI Cadence driver to support data transmission
with bits_per_word values of 16 and 32.

The CIX Sky1 SPI supported patch is added:
https://lore.kernel.org/all/20250919013118.853078-1-jun.guo@cixtech.com/

The patches have been tested on CIX SKY1 platform.

Changes for v3:
- Rebase the dt-bindings modification on top of the latest patches in
  spi/for-next to make the patch more minimal. 

Changes for v2:
- Remove the fifo-width property and add a compatible string for the
  cix sky1 SoC to control the FIFO data width configuration.

Jun Guo (3):
  dt-bindings: spi: spi-cadence: update DT binding docs to support cix
    sky1 SoC
  spi: spi-cadence: supports transmission with bits_per_word of 16 and
    32
  arm64: dts: cix: add a compatible string for the cix sky1 SoC

 .../devicetree/bindings/spi/spi-cadence.yaml  |   1 +
 arch/arm64/boot/dts/cix/sky1.dtsi             |   4 +-
 drivers/spi/spi-cadence.c                     | 106 +++++++++++++++---
 3 files changed, 96 insertions(+), 15 deletions(-)

-- 
2.34.1