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Message-Id: <176189884156.5303.14323602106505981794.b4-ty@kernel.org>
Date: Fri, 31 Oct 2025 13:50:41 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Vinod Koul <vkoul@...nel.org>, 
 Kishon Vijay Abraham I <kishon@...nel.org>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, 
 Lorenzo Pieralisi <lpieralisi@...nel.org>, 
 Krzysztof WilczyƄski <kwilczynski@...nel.org>, 
 Bjorn Helgaas <bhelgaas@...gle.com>, Bjorn Andersson <andersson@...nel.org>, 
 Qiang Yu <qiang.yu@....qualcomm.com>
Cc: linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org, 
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
 linux-pci@...r.kernel.org, Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>, 
 Wenbin Yao <wenbin.yao@....qualcomm.com>, 
 Qiang Yu <quic_qianyu@...cinc.com>, 
 Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
Subject: Re: (subset) [PATCH v5 0/6] PCI: qcom: Add support for Glymur PCIe
 Gen5 x4 and Gen4 x2


On Fri, 17 Oct 2025 18:33:37 -0700, Qiang Yu wrote:
> Glymur is the next generation compute SoC of Qualcomm. This patch series
> aims to add support for the fourth, fifth and sixth PCIe instance on it.
> The fifth PCIe instance on Glymur has a Gen5 4-lane PHY and fourth, fifth
> and sixth PCIe instance have a Gen5 2-lane PHY.
> 
> The device tree changes and whatever driver patches that are not part of
> this patch series will be posted separately after official announcement of
> the SOC.
> 
> [...]

Applied, thanks!

[3/6] dt-bindings: PCI: qcom: Document the Glymur PCIe Controller
      commit: f0b5af98e1b5761095d5186d3a7af5a0991a5cd9

Best regards,
-- 
Manivannan Sadhasivam <mani@...nel.org>


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