[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20251031-optimize_pll_driver-v3-4-92f3b2f36a83@amlogic.com>
Date: Fri, 31 Oct 2025 16:10:11 +0800
From: Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@...nel.org>
To: Neil Armstrong <neil.armstrong@...aro.org>,
Jerome Brunet <jbrunet@...libre.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Kevin Hilman <khilman@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Cc: linux-amlogic@...ts.infradead.org, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Chuan Liu <chuan.liu@...ogic.com>
Subject: [PATCH v3 4/4] clk: amlogic: Optimize PLL enable timing
From: Chuan Liu <chuan.liu@...ogic.com>
l_detect controls the enablement of the PLL lock detection module.
It should remain disabled while the internal PLL circuits are
reaching a steady state; otherwise, the lock signal may be falsely
triggered high.
A 20 us delay has been added before enabling the PLL, so there’s no
need for an additional 10 us delay before enabling current_en.
Currently, only A1 supports both l_detect and current_en, so this
patch will only affect A1.
Signed-off-by: Chuan Liu <chuan.liu@...ogic.com>
---
drivers/clk/meson/clk-pll.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index cdb39a723bd0..c9b941adf688 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -383,6 +383,10 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
if (MESON_PARM_APPLICABLE(&pll->rst))
meson_parm_write(clk->map, &pll->rst, 1);
+ /* Disable the PLL lock-detect module */
+ if (MESON_PARM_APPLICABLE(&pll->l_detect))
+ meson_parm_write(clk->map, &pll->l_detect, 1);
+
/* Enable the pll */
meson_parm_write(clk->map, &pll->en, 1);
@@ -401,20 +405,18 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
* Compared with the previous SoCs, self-adaption current module
* is newly added for A1, keep the new power-on sequence to enable the
* PLL. The sequence is:
- * 1. enable the pll, delay for 10us
+ * 1. enable the pll, delay for 20us
* 2. enable the pll self-adaption current module, delay for 40us
* 3. enable the lock detect module
*/
if (MESON_PARM_APPLICABLE(&pll->current_en)) {
- udelay(10);
meson_parm_write(clk->map, &pll->current_en, 1);
udelay(40);
}
- if (MESON_PARM_APPLICABLE(&pll->l_detect)) {
- meson_parm_write(clk->map, &pll->l_detect, 1);
+ /* Enable the lock-detect module */
+ if (MESON_PARM_APPLICABLE(&pll->l_detect))
meson_parm_write(clk->map, &pll->l_detect, 0);
- }
if (meson_clk_pll_wait_lock(hw)) {
/* disable PLL when PLL lock failed. */
--
2.42.0
Powered by blists - more mailing lists