| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20251031-tcsrcc_glymur-v1-1-0efb031f0ac5@oss.qualcomm.com>
Date: Fri, 31 Oct 2025 15:32:25 +0530
From: Taniya Das <taniya.das@....qualcomm.com>
To: Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Abel Vesa <abel.vesa@...aro.org>,
Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
Cc: Rajendra Nayak <quic_rjendra@...cinc.com>,
Ajit Pandey <ajit.pandey@....qualcomm.com>,
Imran Shaik <imran.shaik@....qualcomm.com>,
Jagadeesh Kona <jagadeesh.kona@....qualcomm.com>,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, Taniya Das <taniya.das@....qualcomm.com>
Subject: [PATCH] clk: qcom: tcsrcc-glymur: Update register offsets for
clock refs
Update the register offsets for all the clock ref branches to match the
new address mapping in the TCSR subsystem.
Fixes: 2c1d6ce4f3da ("clk: qcom: Add TCSR clock driver for Glymur SoC")
Signed-off-by: Taniya Das <taniya.das@....qualcomm.com>
---
drivers/clk/qcom/tcsrcc-glymur.c | 54 ++++++++++++++++++++--------------------
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-glymur.c
index c1f8b6d10b7fd6eaef0149843594fc7eb6a620ec..215bc2ac548da83aec23921ef9a4bd59b6b307bc 100644
--- a/drivers/clk/qcom/tcsrcc-glymur.c
+++ b/drivers/clk/qcom/tcsrcc-glymur.c
@@ -28,10 +28,10 @@ enum {
};
static struct clk_branch tcsr_edp_clkref_en = {
- .halt_reg = 0x1c,
+ .halt_reg = 0x60,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x1c,
+ .enable_reg = 0x60,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_edp_clkref_en",
@@ -45,10 +45,10 @@ static struct clk_branch tcsr_edp_clkref_en = {
};
static struct clk_branch tcsr_pcie_1_clkref_en = {
- .halt_reg = 0x4,
+ .halt_reg = 0x48,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x4,
+ .enable_reg = 0x48,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_1_clkref_en",
@@ -62,10 +62,10 @@ static struct clk_branch tcsr_pcie_1_clkref_en = {
};
static struct clk_branch tcsr_pcie_2_clkref_en = {
- .halt_reg = 0x8,
+ .halt_reg = 0x4c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x8,
+ .enable_reg = 0x4c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_2_clkref_en",
@@ -79,10 +79,10 @@ static struct clk_branch tcsr_pcie_2_clkref_en = {
};
static struct clk_branch tcsr_pcie_3_clkref_en = {
- .halt_reg = 0x10,
+ .halt_reg = 0x54,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x10,
+ .enable_reg = 0x54,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_3_clkref_en",
@@ -96,10 +96,10 @@ static struct clk_branch tcsr_pcie_3_clkref_en = {
};
static struct clk_branch tcsr_pcie_4_clkref_en = {
- .halt_reg = 0x14,
+ .halt_reg = 0x58,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x14,
+ .enable_reg = 0x58,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_4_clkref_en",
@@ -113,10 +113,10 @@ static struct clk_branch tcsr_pcie_4_clkref_en = {
};
static struct clk_branch tcsr_usb2_1_clkref_en = {
- .halt_reg = 0x28,
+ .halt_reg = 0x6c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x28,
+ .enable_reg = 0x6c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_1_clkref_en",
@@ -130,10 +130,10 @@ static struct clk_branch tcsr_usb2_1_clkref_en = {
};
static struct clk_branch tcsr_usb2_2_clkref_en = {
- .halt_reg = 0x2c,
+ .halt_reg = 0x70,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x2c,
+ .enable_reg = 0x70,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_2_clkref_en",
@@ -147,10 +147,10 @@ static struct clk_branch tcsr_usb2_2_clkref_en = {
};
static struct clk_branch tcsr_usb2_3_clkref_en = {
- .halt_reg = 0x30,
+ .halt_reg = 0x74,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x30,
+ .enable_reg = 0x74,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_3_clkref_en",
@@ -164,10 +164,10 @@ static struct clk_branch tcsr_usb2_3_clkref_en = {
};
static struct clk_branch tcsr_usb2_4_clkref_en = {
- .halt_reg = 0x44,
+ .halt_reg = 0x88,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x44,
+ .enable_reg = 0x88,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_4_clkref_en",
@@ -181,10 +181,10 @@ static struct clk_branch tcsr_usb2_4_clkref_en = {
};
static struct clk_branch tcsr_usb3_0_clkref_en = {
- .halt_reg = 0x20,
+ .halt_reg = 0x64,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x20,
+ .enable_reg = 0x64,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb3_0_clkref_en",
@@ -198,10 +198,10 @@ static struct clk_branch tcsr_usb3_0_clkref_en = {
};
static struct clk_branch tcsr_usb3_1_clkref_en = {
- .halt_reg = 0x24,
+ .halt_reg = 0x68,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x24,
+ .enable_reg = 0x68,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb3_1_clkref_en",
@@ -215,10 +215,10 @@ static struct clk_branch tcsr_usb3_1_clkref_en = {
};
static struct clk_branch tcsr_usb4_1_clkref_en = {
- .halt_reg = 0x0,
+ .halt_reg = 0x44,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x0,
+ .enable_reg = 0x44,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb4_1_clkref_en",
@@ -232,10 +232,10 @@ static struct clk_branch tcsr_usb4_1_clkref_en = {
};
static struct clk_branch tcsr_usb4_2_clkref_en = {
- .halt_reg = 0x18,
+ .halt_reg = 0x5c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
- .enable_reg = 0x18,
+ .enable_reg = 0x5c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb4_2_clkref_en",
@@ -268,7 +268,7 @@ static const struct regmap_config tcsr_cc_glymur_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
- .max_register = 0x44,
+ .max_register = 0x94,
.fast_io = true,
};
---
base-commit: 131f3d9446a6075192cdd91f197989d98302faa6
change-id: 20251030-tcsrcc_glymur-dd081857db46
Best regards,
--
Taniya Das <taniya.das@....qualcomm.com>
Powered by blists - more mailing lists