linux-kernel - Re: [PATCH v5 0/2] Add Qualcomm extended CTI support

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Message-ID: <CAJ9a7VjTqBczkdMYXqb1WmDRUYhC--dY6Ky5R=NfUZaYkiWmVw@mail.gmail.com>
Date: Fri, 31 Oct 2025 10:31:57 +0000
From: Mike Leach <mike.leach@...aro.org>
To: Yingchao Deng <yingchao.deng@....qualcomm.com>
Cc: Suzuki K Poulose <suzuki.poulose@....com>, James Clark <james.clark@...aro.org>, 
	Alexander Shishkin <alexander.shishkin@...ux.intel.com>, coresight@...ts.linaro.org, 
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, 
	linux-arm-msm@...r.kernel.org, Tingwei Zhang <tingwei.zhang@....qualcomm.com>, 
	quic_yingdeng@...cinc.com, Jinlong Mao <jinlong.mao@....qualcomm.com>, 
	Jinlong Mao <jinglong.mao@....qualcomm.com>
Subject: Re: [PATCH v5 0/2] Add Qualcomm extended CTI support

Hi,

This set is looking good now and appears to be getting close to being ready.

There are a few minor issues in the second patch and a few items that
need to be confirmed.
1) I note that you removed the code to prevent calling claim/disclaim.
Does this mean that you confirm that you have tested the patch update
for claim tags I posted works on your system?
2) In patch 2 I made some comments in regard to ARCH values - please
confirm that these are accurate and have been tested as working on
your system
3) As mentioned in the comments to patch 2 - you need to update the
docs for the new sysfs selection file you have added

Thanks and Regards

Mike

On Mon, 20 Oct 2025 at 08:12, Yingchao Deng
<yingchao.deng@....qualcomm.com> wrote:
>
> The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI.
> It allows a debugger to send to trigger events to a processor or to send
> a trigger event to one or more processors when a trigger event occurs on
> another processor on the same SoC, or even between SoCs.
>
> QCOM extended CTI supports up to 128 triggers. And some of the register
> offsets are changed.
>
> The commands to configure CTI triggers are the same as ARM's CTI.
>
> Changes in v5:
> 1. Move common part in qcom-cti.h to coresight-cti.h.
> 2. Convert trigger usage fields to dynamic bitmaps and arrays.
> 3. Fix holes in struct cti_config to save some space.
> 4. Revert the previous changes related to the claim tag in
>    cti_enable/disable_hw.
> Link to v4 - https://lore.kernel.org/linux-arm-msm/20250902-extended_cti-v4-1-7677de04b416@oss.qualcomm.com/
>
> Changes in v4:
> 1. Read the DEVARCH registers to identify Qualcomm CTI.
> 2. Add a reg_idx node, and refactor the coresight_cti_reg_show() and
> coresight_cti_reg_store() functions accordingly.
> 3. The register offsets specific to Qualcomm CTI are moved to qcom_cti.h.
> Link to v3 - https://lore.kernel.org/linux-arm-msm/20250722081405.2947294-1-quic_jinlmao@quicinc.com/
>
> Changes in v3:
> 1. Rename is_extended_cti() to of_is_extended_cti().
> 2. Add the missing 'i' when write the CTI trigger registers.
> 3. Convert the multi-line output in sysfs to single line.
> 4. Initialize offset arrays using designated initializer.
> Link to V2 - https://lore.kernel.org/all/20250429071841.1158315-3-quic_jinlmao@quicinc.com/
>
> Changes in V2:
> 1. Add enum for compatible items.
> 2. Move offset arrays to coresight-cti-core
>
> Signed-off-by: Jinlong Mao <jinlong.mao@....qualcomm.com>
> Signed-off-by: Yingchao Deng <yingchao.deng@....qualcomm.com>
> ---
> Yingchao Deng (2):
>       coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays
>       coresight: cti: Add Qualcomm extended CTI support
>
>  drivers/hwtracing/coresight/coresight-cti-core.c   | 144 +++++++++++++---
>  .../hwtracing/coresight/coresight-cti-platform.c   |  16 +-
>  drivers/hwtracing/coresight/coresight-cti-sysfs.c  | 184 +++++++++++++++------
>  drivers/hwtracing/coresight/coresight-cti.h        |  60 ++++++-
>  drivers/hwtracing/coresight/qcom-cti.h             |  29 ++++
>  5 files changed, 346 insertions(+), 87 deletions(-)
> ---
> base-commit: 1fdbb3ff1233e204e26f9f6821ae9c125a055229
> change-id: 20251016-extended_cti-2a426c8894b1
>
> Best regards,
> --
> Yingchao Deng <yingchao.deng@....qualcomm.com>
>


-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK