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Message-ID: <20251102-ultraviolet-cow-of-refinement-ac8fff@kuoka>
Date: Sun, 2 Nov 2025 17:36:08 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: "Rob Herring (Arm)" <robh@...nel.org>
Cc: Moritz Fischer <mdf@...nel.org>, Xu Yilun <yilun.xu@...el.com>,
Tom Rix <trix@...hat.com>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Joel Holdsworth <joel@...webreathe.org.uk>,
linux-fpga@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] dt-bindings: fpga: Convert lattice,ice40-fpga-mgr to DT
schema
On Wed, Oct 29, 2025 at 01:55:01PM -0500, Rob Herring (Arm) wrote:
> +
> +title: Lattice iCE40 FPGA Manager
> +
> +maintainers:
> + - Joel Holdsworth <joel@...webreathe.org.uk>
> +
You miss spi-peripheral-props
> +properties:
> + compatible:
> + const: lattice,ice40-fpga-mgr
> +
> + reg:
> + maxItems: 1
> +
> + spi-max-frequency:
> + minimum: 1000000
> + maximum: 25000000
> +
> + cdone-gpios:
> + maxItems: 1
> + description: GPIO input connected to CDONE pin
> +
> + reset-gpios:
> + maxItems: 1
> + description:
> + Active-low GPIO output connected to CRESET_B pin. Note that unless the
> + GPIO is held low during startup, the FPGA will enter Master SPI mode and
> + drive SCK with a clock signal potentially jamming other devices on the bus
> + until the firmware is loaded.
> +
> +required:
> + - compatible
> + - reg
> + - spi-max-frequency
> + - cdone-gpios
> + - reset-gpios
> +
> +additionalProperties: false
... and here unevaluatedProperties.
Best regards,
Krzysztof
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