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Message-ID: <lf5nlalqrx6zirhzxf7z4nfqwx5lljwot6izj66ljm57pbz3bd@t7cipoonvy4o>
Date: Sun, 2 Nov 2025 11:47:47 -0600
From: Bjorn Andersson <andersson@...nel.org>
To: Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>
Cc: Wenmeng Liu <wenmeng.liu@....qualcomm.com>,
Robert Foss <rfoss@...nel.org>, Todor Tomov <todor.too@...il.com>,
Bryan O'Donoghue <bryan.odonoghue@...aro.org>, Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Konrad Dybcio <konradybcio@...nel.org>,
linux-media@...r.kernel.org, linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/3] arm64: dts: qcom: sm6150: Add camss node
On Thu, Oct 16, 2025 at 04:48:02PM +0300, Vladimir Zapolskiy wrote:
> On 10/16/25 13:22, Wenmeng Liu wrote:
> > Add node for the SM6150 camera subsystem.
> >
> > Signed-off-by: Wenmeng Liu <wenmeng.liu@....qualcomm.com>
> > ---
> > arch/arm64/boot/dts/qcom/sm6150.dtsi | 121 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 121 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi
> > index 3d2a1cb02b628a5db7ca14bea784429be5a020f9..ebfb336439b4fdfa567c0e011cd4da88a6290dfd 100644
> > --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi
> > @@ -3646,6 +3646,127 @@ videocc: clock-controller@...0000 {
> > #power-domain-cells = <1>;
> > };
> > + camss: isp@...3000 {
> > + compatible = "qcom,sm6150-camss";
> > +
> > + reg = <0x0 0x0acb3000 0x0 0x1000>,
> > + <0x0 0x0acba000 0x0 0x1000>,
> > + <0x0 0x0acc8000 0x0 0x1000>,
> > + <0x0 0x0ac65000 0x0 0x1000>,
> > + <0x0 0x0ac66000 0x0 0x1000>,
> > + <0x0 0x0ac67000 0x0 0x1000>,
> > + <0x0 0x0acaf000 0x0 0x4000>,
> > + <0x0 0x0acb6000 0x0 0x4000>,
> > + <0x0 0x0acc4000 0x0 0x4000>;
> > + reg-names = "csid0",
> > + "csid1",
> > + "csid_lite",
> > + "csiphy0",
> > + "csiphy1",
> > + "csiphy2",
> > + "vfe0",
> > + "vfe1",
> > + "vfe_lite";
> > +
> > + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> > + <&camcc CAM_CC_CPAS_AHB_CLK>,
> > + <&camcc CAM_CC_CSIPHY0_CLK>,
> > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> > + <&camcc CAM_CC_CSIPHY1_CLK>,
> > + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
> > + <&camcc CAM_CC_CSIPHY2_CLK>,
> > + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
> > + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> > + <&camcc CAM_CC_SOC_AHB_CLK>,
> > + <&camcc CAM_CC_IFE_0_CLK>,
> > + <&camcc CAM_CC_IFE_0_AXI_CLK>,
> > + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
> > + <&camcc CAM_CC_IFE_0_CSID_CLK>,
> > + <&camcc CAM_CC_IFE_1_CLK>,
> > + <&camcc CAM_CC_IFE_1_AXI_CLK>,
> > + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
> > + <&camcc CAM_CC_IFE_1_CSID_CLK>,
> > + <&camcc CAM_CC_IFE_LITE_CLK>,
> > + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
> > + <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
> > +
> > + clock-names = "camnoc_axi",
> > + "cpas_ahb",
> > + "csiphy0",
> > + "csiphy0_timer",
> > + "csiphy1",
> > + "csiphy1_timer",
> > + "csiphy2",
> > + "csiphy2_timer",
> > + "gcc_axi_hf",
> > + "soc_ahb",
> > + "vfe0",
> > + "vfe0_axi",
> > + "vfe0_cphy_rx",
> > + "vfe0_csid",
> > + "vfe1",
> > + "vfe1_axi",
> > + "vfe1_cphy_rx",
> > + "vfe1_csid",
> > + "vfe_lite",
> > + "vfe_lite_cphy_rx",
> > + "vfe_lite_csid";
> > +
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mmss_noc MASTER_CAMNOC_HF0 QCOM_ICC_TAG_ALWAYS
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> > + interconnect-names = "ahb",
> > + "hf_mnoc";
> > +
> > + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
> > + interrupt-names = "csid0",
> > + "csid1",
> > + "csid_lite",
> > + "csiphy0",
> > + "csiphy1",
> > + "csiphy2",
> > + "vfe0",
> > + "vfe1",
> > + "vfe_lite";
> > +
> > + iommus = <&apps_smmu 0x820 0x40>;
> > +
> > + power-domains = <&camcc IFE_0_GDSC>,
> > + <&camcc IFE_1_GDSC>,
> > + <&camcc TITAN_TOP_GDSC>;
> > + power-domain-names = "ife0",
> > + "ife1",
> > + "top";
> > +
> > + status = "disabled";
>
> Please remove empty lines between properties all above.
>
The empty lines between groups of properties makes this massive chunk of
properties easier to read, at no real cost.
The one exception is the extra empty line between clocks and
clock-names, but there's no need to resubmit for that.
Regards,
Bjorn
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > + };
> > +
> > + port@1 {
> > + reg = <1>;
> > + };
> > +
> > + port@2 {
> > + reg = <2>;
> > + };
> > + };
> > + };
> > +
> > camcc: clock-controller@...0000 {
> > compatible = "qcom,qcs615-camcc";
> > reg = <0 0x0ad00000 0 0x10000>;
> >
>
> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>
>
> --
> Best wishes,
> Vladimir
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