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Message-Id: <20251103-dt-bindings-pci-qcom-v1-4-c0f6041abf9b@linaro.org>
Date: Mon, 03 Nov 2025 16:14:44 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Bjorn Helgaas <bhelgaas@...gle.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kwilczynski@...nel.org>,
Manivannan Sadhasivam <mani@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Bjorn Andersson <andersson@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: [PATCH 04/12] dt-bindings: PCI: qcom,pcie-qcs404: Move QCS404 to
dedicated schema
Move QCS404 PCIe devices from qcom,pcie.yaml binding to a dedicated file
to make reviewing and maintenance easier.
New schema is equivalent to the old one with few changes:
- Adding a required compatible, which is actually redundant.
- Drop the really obvious comments next to clock/reg/reset-names items.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
---
.../devicetree/bindings/pci/qcom,pcie-qcs404.yaml | 131 +++++++++++++++++++++
.../devicetree/bindings/pci/qcom,pcie.yaml | 33 ------
2 files changed, 131 insertions(+), 33 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-qcs404.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-qcs404.yaml
new file mode 100644
index 000000000000..99b3ed43b87c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-qcs404.yaml
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-qcs404.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QCS404 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@...nel.org>
+ - Manivannan Sadhasivam <mani@...nel.org>
+
+properties:
+ compatible:
+ enum:
+ - qcom,pcie-qcs404
+
+ reg:
+ maxItems: 4
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: elbi
+ - const: parf
+ - const: config
+
+ clocks:
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: iface # AHB clock
+ - const: aux
+ - const: master_bus # AXI Master clock
+ - const: slave_bus # AXI Slave clock
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ items:
+ - const: msi
+
+ resets:
+ maxItems: 6
+
+ reset-names:
+ items:
+ - const: axi_m # AXI Master reset
+ - const: axi_s # AXI Slave reset
+ - const: axi_m_sticky # AXI Master Sticky reset
+ - const: pipe_sticky
+ - const: pwr
+ - const: ahb
+
+required:
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-qcs404.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pcie@...00000 {
+ compatible = "qcom,pcie-qcs404";
+ reg = <0x10000000 0xf1d>,
+ <0x10000f20 0xa8>,
+ <0x07780000 0x2000>,
+ <0x10001000 0x2000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */
+ <0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */
+
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
+ clock-names = "iface", "aux", "master_bus", "slave_bus";
+
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ phys = <&pcie_phy>;
+ phy-names = "pciephy";
+
+ perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
+
+ resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>,
+ <&gcc GCC_PCIE_0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE_0_BCR>,
+ <&gcc GCC_PCIE_0_AHB_ARES>;
+ reset-names = "axi_m",
+ "axi_s",
+ "axi_m_sticky",
+ "pipe_sticky",
+ "pwr",
+ "ahb";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 68cae47c2ef6..df58e52cc0b9 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -29,7 +29,6 @@ properties:
- qcom,pcie-ipq8074-gen3
- qcom,pcie-ipq9574
- qcom,pcie-msm8996
- - qcom,pcie-qcs404
- items:
- enum:
- qcom,pcie-ipq5332
@@ -149,7 +148,6 @@ allOf:
- qcom,pcie-ipq8064
- qcom,pcie-ipq8064v2
- qcom,pcie-ipq8074
- - qcom,pcie-qcs404
then:
properties:
reg:
@@ -483,35 +481,6 @@ allOf:
- const: msi7
- const: global
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-qcs404
- then:
- properties:
- clocks:
- minItems: 4
- maxItems: 4
- clock-names:
- items:
- - const: iface # AHB clock
- - const: aux # Auxiliary clock
- - const: master_bus # AXI Master clock
- - const: slave_bus # AXI Slave clock
- resets:
- minItems: 6
- maxItems: 6
- reset-names:
- items:
- - const: axi_m # AXI Master reset
- - const: axi_s # AXI Slave reset
- - const: axi_m_sticky # AXI Master Sticky reset
- - const: pipe_sticky # PIPE sticky reset
- - const: pwr # PWR reset
- - const: ahb # AHB reset
-
- if:
not:
properties:
@@ -526,7 +495,6 @@ allOf:
- qcom,pcie-ipq8074
- qcom,pcie-ipq8074-gen3
- qcom,pcie-ipq9574
- - qcom,pcie-qcs404
then:
required:
- power-domains
@@ -588,7 +556,6 @@ allOf:
- qcom,pcie-ipq4019
- qcom,pcie-ipq8064
- qcom,pcie-ipq8064-v2
- - qcom,pcie-qcs404
then:
properties:
interrupts:
--
2.48.1
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