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Message-ID: <CADnq5_PwPiMT+oh7ccLn+aL_zTgA0cFUQRiKQEM3V6AZHvBrOQ@mail.gmail.com>
Date: Mon, 3 Nov 2025 16:31:38 -0500
From: Alex Deucher <alexdeucher@...il.com>
To: "Yo-Jung Leo Lin (AMD)" <Leo.Lin@....com>
Cc: Alex Deucher <alexander.deucher@....com>,
Christian König <christian.koenig@....com>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>, Jonathan Corbet <corbet@....net>, amd-gfx@...ts.freedesktop.org,
dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
linux-doc@...r.kernel.org, anson.tsao@....com, superm1@...nel.org
Subject: Re: [PATCH 3/5] drm/amdgpu: add UMA allocation setting helpers
On Mon, Nov 3, 2025 at 3:11 AM Yo-Jung Leo Lin (AMD) <Leo.Lin@....com> wrote:
>
> On some platforms, UMA allocation size can be set using the ATCS
> methods. Add helper functions to interact with this functionality.
>
> Co-developed-by: Mario Limonciello (AMD) <superm1@...nel.org>
> Signed-off-by: Mario Limonciello (AMD) <superm1@...nel.org>
> Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@....com>
Reviewed-by: Alex Deucher <alexander.deucher@....com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 ++++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 43 ++++++++++++++++++++++++++++++++
> drivers/gpu/drm/amd/include/amd_acpi.h | 30 ++++++++++++++++++++++
> 3 files changed, 80 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index a5574e84694b..3de520f0b5b4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1686,12 +1686,14 @@ int amdgpu_acpi_init(struct amdgpu_device *adev);
> void amdgpu_acpi_fini(struct amdgpu_device *adev);
> bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
> bool amdgpu_acpi_is_power_shift_control_supported(void);
> +bool amdgpu_acpi_is_set_uma_allocation_size_supported(void);
> int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
> u8 perf_req, bool advertise);
> int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
> u8 dev_state, bool drv_state);
> int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev,
> enum amdgpu_ss ss_state);
> +int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type);
> int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
> int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
> u64 *tmr_size);
> @@ -1720,6 +1722,7 @@ static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { re
> static inline void amdgpu_acpi_detect(void) { }
> static inline void amdgpu_acpi_release(void) { }
> static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
> +static inline bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) { return false; }
> static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
> u8 dev_state, bool drv_state) { return 0; }
> static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev,
> @@ -1727,6 +1730,10 @@ static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev,
> {
> return 0;
> }
> +int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type)
> +{
> + return -EINVAL;
> +}
> static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { }
> #endif
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> index 0743fd8620e4..d53f7b33d619 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> @@ -669,6 +669,11 @@ bool amdgpu_acpi_is_power_shift_control_supported(void)
> return amdgpu_acpi_priv.atcs.functions.power_shift_control;
> }
>
> +bool amdgpu_acpi_is_set_uma_allocation_size_supported(void)
> +{
> + return amdgpu_acpi_priv.atcs.functions.set_uma_allocation_size;
> +}
> +
> /**
> * amdgpu_acpi_pcie_notify_device_ready
> *
> @@ -909,6 +914,44 @@ static struct amdgpu_numa_info *amdgpu_acpi_get_numa_info(uint32_t pxm)
> }
> #endif
>
> +/**
> + * amdgpu_acpi_set_uma_allocation_size - Set Unified Memory Architecture allocation size via ACPI
> + * @adev: Pointer to the amdgpu_device structure
> + * @index: Index specifying the UMA allocation
> + * @type: Type of UMA allocation
> + *
> + * This function configures the UMA allocation size for the specified device
> + * using ACPI methods. The allocation is determined by the provided index and type.
> + * Returns 0 on success or a negative error code on failure.
> + */
> +int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type)
> +{
> + struct atcs_set_uma_allocation_size_input atcs_input;
> + struct amdgpu_atcs *atcs = &amdgpu_acpi_priv.atcs;
> + struct acpi_buffer params;
> + union acpi_object *info;
> +
> + if (!amdgpu_acpi_is_set_uma_allocation_size_supported())
> + return -EINVAL;
> +
> + atcs_input.size = sizeof(struct atcs_set_uma_allocation_size_input);
> + atcs_input.uma_size_index = index;
> + atcs_input.uma_size_type = type;
> +
> + params.length = sizeof(struct atcs_set_uma_allocation_size_input);
> + params.pointer = &atcs_input;
> +
> + info = amdgpu_atcs_call(atcs, ATCS_FUNCTION_SET_UMA_ALLOCATION_SIZE, ¶ms);
> + if (!info) {
> + drm_err(adev_to_drm(adev), "ATCS UMA allocation size update failed\n");
> + return -EIO;
> + }
> +
> + kfree(info);
> +
> + return 0;
> +}
> +
> /**
> * amdgpu_acpi_get_node_id - obtain the NUMA node id for corresponding amdgpu
> * acpi device handle
> diff --git a/drivers/gpu/drm/amd/include/amd_acpi.h b/drivers/gpu/drm/amd/include/amd_acpi.h
> index e582339e8e8e..84933c07f720 100644
> --- a/drivers/gpu/drm/amd/include/amd_acpi.h
> +++ b/drivers/gpu/drm/amd/include/amd_acpi.h
> @@ -24,6 +24,8 @@
> #ifndef AMD_ACPI_H
> #define AMD_ACPI_H
>
> +#include <linux/types.h>
> +
> #define ACPI_AC_CLASS "ac_adapter"
>
> struct atif_verify_interface {
> @@ -112,6 +114,17 @@ struct atcs_pwr_shift_input {
> u8 drv_state; /* 0 = operational, 1 = not operational */
> } __packed;
>
> +struct atcs_get_uma_size_output {
> + u16 size; /* structure size in bytes (includes size field) */
> + u32 uma_size_mb; /* allocated UMA size in MB */
> +} __packed;
> +
> +struct atcs_set_uma_allocation_size_input {
> + u16 size; /* structure size in bytes (includes size field) */
> + u8 uma_size_index; /* UMA size index */
> + u8 uma_size_type; /* UMA size type */
> +} __packed;
> +
> /* AMD hw uses four ACPI control methods:
> * 1. ATIF
> * ARG0: (ACPI_INTEGER) function code
> @@ -494,4 +507,21 @@ struct atcs_pwr_shift_input {
> * OUTPUT: none
> */
>
> +#define ATCS_FUNCTION_GET_UMA_SIZE 0x6
> +/* ARG0: ATCS_FUNCTION_GET_UMA_SIZE
> + * ARG1: none
> + * OUTPUT:
> + * WORD - structure size in bytes (includes size field)
> + * DWORD - allocated UMA size in MB
> + */
> +
> +#define ATCS_FUNCTION_SET_UMA_ALLOCATION_SIZE 0xA
> +/* ARG0: ATCS_FUNCTION_SET_UMA_ALLOCATION_SIZE
> + * ARG1:
> + * WORD - structure size in bytes (includes size field)
> + * BYTE - UMA size index
> + * BYTE - UMA size type
> + * OUTPUT: none
> + */
> +
> #endif
>
> --
> 2.43.0
>
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