linux-kernel - Re: [PATCH v9 4/6] i3c: master: svc: Add basic HDR mode support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <aQhh2zZVxh1oVuJz@smile.fi.intel.com>
Date: Mon, 3 Nov 2025 10:03:39 +0200
From: Andy Shevchenko <andriy.shevchenko@...el.com>
To: Frank Li <Frank.Li@....com>
Cc: Alexandre Belloni <alexandre.belloni@...tlin.com>,
	Miquel Raynal <miquel.raynal@...tlin.com>,
	Jonathan Cameron <jic23@...nel.org>,
	David Lechner <dlechner@...libre.com>,
	Nuno Sá <nuno.sa@...log.com>,
	Andy Shevchenko <andy@...nel.org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, linux-i3c@...ts.infradead.org,
	linux-kernel@...r.kernel.org, imx@...ts.linux.dev,
	linux-iio@...r.kernel.org, joshua.yeong@...rfivetech.com,
	devicetree@...r.kernel.org, linux@...ck-us.net,
	Carlos Song <carlos.song@....com>
Subject: Re: [PATCH v9 4/6] i3c: master: svc: Add basic HDR mode support

On Fri, Oct 31, 2025 at 12:39:16PM -0400, Frank Li wrote:
> Add basic HDR mode support for the svs I3C master driver.
> 
> Only support for private transfers and does not support sending CCC
> commands in HDR mode.
> 
> Key differences:
> - HDR uses commands (0x00-0x7F for write, 0x80-0xFF for read) to
> distinguish transfer direction.
> - HDR read/write commands must be written to FIFO before issuing the I3C
> address command. The hardware automatically sends the standard CCC command
> to enter HDR mode.
> - HDR exit pattern must be sent instead of send a stop after transfer
> completion.
> - Read/write data size must be an even number.

...

>  static bool svc_cmd_is_read(u32 rnw_cmd, u32 type)
>  {
> -	return rnw_cmd;
> +	return (type == SVC_I3C_MCTRL_TYPE_DDR) ? !!(rnw_cmd & 0x80) : rnw_cmd;

This seems confusing. Either !! is redundant (which is actually the case) or
I don't know what the idea behind this.

> +}

...

> +static void svc_i3c_master_emit_force_exit(struct svc_i3c_master *master)
> +{
> +	u32 reg;
> +
> +	writel(SVC_I3C_MCTRL_REQUEST_FORCE_EXIT, master->regs + SVC_I3C_MCTRL);
> +
> +	/*
> +	 * Not need check error here because it is never happen at hardware. IP

If you move 'IP' to the next line it will be better to read.

> +	 * just wait for few fclk cycle to complete DDR exit pattern. Even
> +	 * though fclk stop, timeout happen here, the whole data actually
> +	 * already finish transfer. The next command will be timeout because
> +	 * wrong hardware state.
> +	 */
> +	readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, reg,
> +				  SVC_I3C_MSTATUS_MCTRLDONE(reg), 0, 1000);
> +
> +	/*
> +	 * This delay is necessary after the emission of a stop, otherwise eg.
> +	 * repeating IBIs do not get detected. There is a note in the manual
> +	 * about it, stating that the stop condition might not be settled
> +	 * correctly if a start condition follows too rapidly.
> +	 */
> +	udelay(1);
>  }

-- 
With Best Regards,
Andy Shevchenko