linux-kernel - Re: [PATCH v1] LoongArch: Refine init_hw_perf

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Message-ID: <CAAhV-H6uRnP6MD7aV0fC-uL+rihuSDw=Opmx=0keQ9gFp9ERhw@mail.gmail.com>
Date: Mon, 3 Nov 2025 17:09:50 +0800
From: Huacai Chen <chenhuacai@...nel.org>
To: Tiezhu Yang <yangtiezhu@...ngson.cn>
Cc: loongarch@...ts.linux.dev, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1] LoongArch: Refine init_hw_perf_events()

Applied without rename loongson to loongson64, because loongson32 and
loongson64 have different event numbers, they need to be
distinguished.

Huacai

On Tue, Oct 14, 2025 at 3:02 PM Tiezhu Yang <yangtiezhu@...ngson.cn> wrote:
>
> (1) Use the existing CPUCFG6_PMNUM_SHIFT macro definition instead of
> the magic value 4 to get the PMU number.
>
> (2) Detect the value of PMU bits via CPUCFG instruction according to
> the ISA manual instead of hard-coded as 64, because the value may be
> different for various microarchitectures.
>
> (3) Rename the PMU name without the postfix 64 due to it is redundant
> and may be inaccurate.
>
> Link: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_cpucfg
> Signed-off-by: Tiezhu Yang <yangtiezhu@...ngson.cn>
> ---
>  arch/loongarch/include/asm/loongarch.h | 1 +
>  arch/loongarch/kernel/perf_event.c     | 8 +++++---
>  2 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
> index 09dfd7eb406e..89343b1a526f 100644
> --- a/arch/loongarch/include/asm/loongarch.h
> +++ b/arch/loongarch/include/asm/loongarch.h
> @@ -128,6 +128,7 @@
>  #define  CPUCFG6_PMNUM                 GENMASK(7, 4)
>  #define  CPUCFG6_PMNUM_SHIFT           4
>  #define  CPUCFG6_PMBITS                        GENMASK(13, 8)
> +#define  CPUCFG6_PMBITS_SHIFT          8
>  #define  CPUCFG6_UPM                   BIT(14)
>
>  #define LOONGARCH_CPUCFG16             0x10
> diff --git a/arch/loongarch/kernel/perf_event.c b/arch/loongarch/kernel/perf_event.c
> index 8ad098703488..ee5404d28423 100644
> --- a/arch/loongarch/kernel/perf_event.c
> +++ b/arch/loongarch/kernel/perf_event.c
> @@ -846,18 +846,20 @@ static const struct loongarch_perf_event *loongarch_pmu_map_raw_event(u64 config
>  static int __init init_hw_perf_events(void)
>  {
>         int counters;
> +       int bits;
>
>         if (!cpu_has_pmp)
>                 return -ENODEV;
>
>         pr_info("Performance counters: ");
> -       counters = ((read_cpucfg(LOONGARCH_CPUCFG6) & CPUCFG6_PMNUM) >> 4) + 1;
> +       counters = ((read_cpucfg(LOONGARCH_CPUCFG6) & CPUCFG6_PMNUM) >> CPUCFG6_PMNUM_SHIFT) + 1;
> +       bits = ((read_cpucfg(LOONGARCH_CPUCFG6) & CPUCFG6_PMBITS) >> CPUCFG6_PMBITS_SHIFT) + 1;
>
>         loongarch_pmu.num_counters = counters;
>         loongarch_pmu.max_period = (1ULL << 63) - 1;
>         loongarch_pmu.valid_count = (1ULL << 63) - 1;
>         loongarch_pmu.overflow = 1ULL << 63;
> -       loongarch_pmu.name = "loongarch/loongson64";
> +       loongarch_pmu.name = "loongarch/loongson";
>         loongarch_pmu.read_counter = loongarch_pmu_read_counter;
>         loongarch_pmu.write_counter = loongarch_pmu_write_counter;
>         loongarch_pmu.map_raw_event = loongarch_pmu_map_raw_event;
> @@ -867,7 +869,7 @@ static int __init init_hw_perf_events(void)
>         on_each_cpu(reset_counters, NULL, 1);
>
>         pr_cont("%s PMU enabled, %d %d-bit counters available to each CPU.\n",
> -                       loongarch_pmu.name, counters, 64);
> +                       loongarch_pmu.name, counters, bits);
>
>         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
>
> --
> 2.42.0
>