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Message-ID: <8f582a2d-a3ef-4b47-82e1-c8f2e4066c12@kernel.org>
Date: Tue, 4 Nov 2025 09:22:26 -0600
From: Mario Limonciello <superm1@...nel.org>
To: Lizhi Hou <lizhi.hou@....com>, ogabbay@...nel.org,
quic_jhugo@...cinc.com, maciej.falkowski@...ux.intel.com,
dri-devel@...ts.freedesktop.org
Cc: linux-kernel@...r.kernel.org, max.zhen@....com, sonal.santan@....com
Subject: Re: [PATCH 1/3] accel/amdxdna: Add hardware specific attributes
On 11/4/25 12:25 AM, Lizhi Hou wrote:
> Add three hardware specific attributes to describe device capabilities:
> hwctx_limit: The maximum number of hardware context supported.
> max_tops: The maximum TOPS supported.
> curr_tops: The TOPS achievable with the current power and frequency
> configuration.
>
> Signed-off-by: Lizhi Hou <lizhi.hou@....com>
Reviewed-by: Mario Limonciello (AMD) <superm1@...nel.org>
> ---
> drivers/accel/amdxdna/aie2_pci.h | 3 +++
> drivers/accel/amdxdna/aie2_smu.c | 11 +++++++++++
> drivers/accel/amdxdna/npu1_regs.c | 1 +
> drivers/accel/amdxdna/npu2_regs.c | 1 +
> drivers/accel/amdxdna/npu4_regs.c | 1 +
> drivers/accel/amdxdna/npu5_regs.c | 1 +
> drivers/accel/amdxdna/npu6_regs.c | 1 +
> 7 files changed, 19 insertions(+)
>
> diff --git a/drivers/accel/amdxdna/aie2_pci.h b/drivers/accel/amdxdna/aie2_pci.h
> index 6cc24641d3db..a79f4f71ff6b 100644
> --- a/drivers/accel/amdxdna/aie2_pci.h
> +++ b/drivers/accel/amdxdna/aie2_pci.h
> @@ -195,6 +195,8 @@ struct amdxdna_dev_hdl {
> u32 clk_gating;
> u32 npuclk_freq;
> u32 hclk_freq;
> + u32 max_tops;
> + u32 curr_tops;
>
> /* Mailbox and the management channel */
> struct mailbox *mbox;
> @@ -246,6 +248,7 @@ struct amdxdna_dev_priv {
> u32 mbox_dev_addr;
> /* If mbox_size is 0, use BAR size. See MBOX_SIZE macro */
> u32 mbox_size;
> + u32 hwctx_limit;
> u32 sram_dev_addr;
> struct aie2_bar_off_pair sram_offs[SRAM_MAX_INDEX];
> struct aie2_bar_off_pair psp_regs_off[PSP_MAX_REGS];
> diff --git a/drivers/accel/amdxdna/aie2_smu.c b/drivers/accel/amdxdna/aie2_smu.c
> index 7f292a615ed8..11c0e9e7b03a 100644
> --- a/drivers/accel/amdxdna/aie2_smu.c
> +++ b/drivers/accel/amdxdna/aie2_smu.c
> @@ -23,6 +23,13 @@
> #define AIE2_SMU_SET_SOFT_DPMLEVEL 0x7
> #define AIE2_SMU_SET_HARD_DPMLEVEL 0x8
>
> +#define NPU4_DPM_TOPS(ndev, dpm_level) \
> +({ \
> + typeof(ndev) _ndev = ndev; \
> + (4096 * (_ndev)->total_col * \
> + (_ndev)->priv->dpm_clk_tbl[dpm_level].hclk / 1000000); \
> +})
> +
> static int aie2_smu_exec(struct amdxdna_dev_hdl *ndev, u32 reg_cmd,
> u32 reg_arg, u32 *out)
> {
> @@ -84,6 +91,8 @@ int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
> amdxdna_pm_suspend_put(ndev->xdna);
> ndev->hclk_freq = freq;
> ndev->dpm_level = dpm_level;
> + ndev->max_tops = 2 * ndev->total_col;
> + ndev->curr_tops = ndev->max_tops * freq / 1028;
>
> XDNA_DBG(ndev->xdna, "MP-NPU clock %d, H clock %d\n",
> ndev->npuclk_freq, ndev->hclk_freq);
> @@ -121,6 +130,8 @@ int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
> ndev->npuclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].npuclk;
> ndev->hclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].hclk;
> ndev->dpm_level = dpm_level;
> + ndev->max_tops = NPU4_DPM_TOPS(ndev, ndev->max_dpm_level);
> + ndev->curr_tops = NPU4_DPM_TOPS(ndev, dpm_level);
>
> XDNA_DBG(ndev->xdna, "MP-NPU clock %d, H clock %d\n",
> ndev->npuclk_freq, ndev->hclk_freq);
> diff --git a/drivers/accel/amdxdna/npu1_regs.c b/drivers/accel/amdxdna/npu1_regs.c
> index 4a43d02404d1..ec407f3b48fc 100644
> --- a/drivers/accel/amdxdna/npu1_regs.c
> +++ b/drivers/accel/amdxdna/npu1_regs.c
> @@ -79,6 +79,7 @@ static const struct amdxdna_dev_priv npu1_dev_priv = {
> .mbox_dev_addr = NPU1_MBOX_BAR_BASE,
> .mbox_size = 0, /* Use BAR size */
> .sram_dev_addr = NPU1_SRAM_BAR_BASE,
> + .hwctx_limit = 6,
> .sram_offs = {
> DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU1_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
> DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU1_SRAM, MPNPU_SRAM_I2X_MAILBOX_15),
> diff --git a/drivers/accel/amdxdna/npu2_regs.c b/drivers/accel/amdxdna/npu2_regs.c
> index 97df2f09356a..86f87d0d1354 100644
> --- a/drivers/accel/amdxdna/npu2_regs.c
> +++ b/drivers/accel/amdxdna/npu2_regs.c
> @@ -72,6 +72,7 @@ static const struct amdxdna_dev_priv npu2_dev_priv = {
> .mbox_dev_addr = NPU2_MBOX_BAR_BASE,
> .mbox_size = 0, /* Use BAR size */
> .sram_dev_addr = NPU2_SRAM_BAR_BASE,
> + .hwctx_limit = 16,
> .sram_offs = {
> DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU2_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
> DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU2_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),
> diff --git a/drivers/accel/amdxdna/npu4_regs.c b/drivers/accel/amdxdna/npu4_regs.c
> index 5a4ed0c363f8..d90777275a9f 100644
> --- a/drivers/accel/amdxdna/npu4_regs.c
> +++ b/drivers/accel/amdxdna/npu4_regs.c
> @@ -99,6 +99,7 @@ static const struct amdxdna_dev_priv npu4_dev_priv = {
> .mbox_dev_addr = NPU4_MBOX_BAR_BASE,
> .mbox_size = 0, /* Use BAR size */
> .sram_dev_addr = NPU4_SRAM_BAR_BASE,
> + .hwctx_limit = 16,
> .sram_offs = {
> DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU4_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
> DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU4_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),
> diff --git a/drivers/accel/amdxdna/npu5_regs.c b/drivers/accel/amdxdna/npu5_regs.c
> index dadd72df6263..75ad97f0b937 100644
> --- a/drivers/accel/amdxdna/npu5_regs.c
> +++ b/drivers/accel/amdxdna/npu5_regs.c
> @@ -72,6 +72,7 @@ static const struct amdxdna_dev_priv npu5_dev_priv = {
> .mbox_dev_addr = NPU5_MBOX_BAR_BASE,
> .mbox_size = 0, /* Use BAR size */
> .sram_dev_addr = NPU5_SRAM_BAR_BASE,
> + .hwctx_limit = 16,
> .sram_offs = {
> DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU5_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
> DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU5_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),
> diff --git a/drivers/accel/amdxdna/npu6_regs.c b/drivers/accel/amdxdna/npu6_regs.c
> index f73f92869b23..758dc013fe13 100644
> --- a/drivers/accel/amdxdna/npu6_regs.c
> +++ b/drivers/accel/amdxdna/npu6_regs.c
> @@ -72,6 +72,7 @@ static const struct amdxdna_dev_priv npu6_dev_priv = {
> .mbox_dev_addr = NPU6_MBOX_BAR_BASE,
> .mbox_size = 0, /* Use BAR size */
> .sram_dev_addr = NPU6_SRAM_BAR_BASE,
> + .hwctx_limit = 16,
> .sram_offs = {
> DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
> DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),
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