linux-kernel - Re: [PATCH] arm64: dts: qcom: kodiak: add coresight nodes

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Message-ID: <133a1f4a-c578-479b-8906-0a70b8a74947@oss.qualcomm.com>
Date: Tue, 4 Nov 2025 09:50:28 +0800
From: Jie Gan <jie.gan@....qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
 <conor+dt@...nel.org>,
        Tingwei Zhang <tingwei.zhang@....qualcomm.com>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: kodiak: add coresight nodes



On 11/3/2025 9:15 PM, Konrad Dybcio wrote:
> On 11/3/25 9:35 AM, Jie Gan wrote:
>> Add TPDM, TPDA, CTI and funnel coresight devices for AOSS and QDSS
>> blocks.
>>
>> Signed-off-by: Jie Gan <jie.gan@....qualcomm.com>
>> ---
>>   arch/arm64/boot/dts/qcom/kodiak.dtsi | 290 +++++++++++++++++++++++++++++++++++
>>   1 file changed, 290 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
>> index 3ef61af2ed8a..09aba1645408 100644
>> --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
>> @@ -3338,6 +3338,85 @@ stm_out: endpoint {
>>   			};
>>   		};
>>   
>> +		tpda@...4000 {
>> +			compatible = "qcom,coresight-tpda", "arm,primecell";
>> +			reg = <0x0 0x06004000 0x0 0x1000>;
>> +
>> +			clocks = <&aoss_qmp>;
>> +			clock-names = "apb_pclk";
>> +
>> +			in-ports {
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +
>> +				port@1c {
>> +					reg = <28>;
> 
> Please use hex in 'reg' (just like you did in the unit address above)
> 
>> +					qdss_tpda_in28: endpoint {
> 
> and leave a \n between the last property and the following subnodes
> 
> [...]
> 

will fix it.


> 
>> +		cti@...0000 {
>> +			compatible = "arm,coresight-cti", "arm,primecell";
>> +			reg = <0x0 0x06010000 0x0 0x1000>;
>> +
>> +			clocks = <&aoss_qmp>;
>> +			clock-names = "apb_pclk";
> 
> I see 15 more CTI instances following this one at a 0x1000 stride,
> followed by a TPIU at 0x06040000.
>

I defined this CTI device solely because it manages debug behaviors for 
STM, ETF, and ETR devices, which are already supported in the upstream 
kernel.

For other CTI devices in QDSS block, they are related to other blocks 
which are not included in current patch. May introduce them in the future.

Thanks,
Jie


> Actually a whole lot more debugging hardware. This patchset looks
> tailored for debugging AOSS< as you briefly mentioned in the commit
> message.
> 
> Would it be beneficial or useful to (perhaps in a separate series)
> extend the support for those?
> 
> FWIW the various register bases and field sizes correspond to what I
> can see in the docs, I can't speak for the port numbers. Please just
> fix up the style issues I mentioned above.
> 
> Konrad