Message-ID: <20251104-enthusiastic-cream-gibbon-0e7b88@kuoka>
Date: Tue, 4 Nov 2025 09:11:29 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Peter Griffin <peter.griffin@...aro.org>
Cc: Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Alim Akhtar <alim.akhtar@...sung.com>, André Draszik <andre.draszik@...aro.org>, 
	Tudor Ambarus <tudor.ambarus@...aro.org>, Michael Turquette <mturquette@...libre.com>, 
	Stephen Boyd <sboyd@...nel.org>, Sam Protsenko <semen.protsenko@...aro.org>, 
	Sylwester Nawrocki <s.nawrocki@...sung.com>, Chanwoo Choi <cw00.choi@...sung.com>, 
	Will McVicker <willmcvicker@...gle.com>, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, 
	linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org, 
	kernel-team@...roid.com
Subject: Re: [PATCH v3 1/4] dt-bindings: clock: google,gs101-clock: add
 samsung,sysreg property as required

On Mon, Nov 03, 2025 at 01:49:53PM +0000, Peter Griffin wrote:
> Hi Krzysztof,
> 
> Thanks for the review feedback!
> 
> On Mon, 3 Nov 2025 at 09:41, Krzysztof Kozlowski <krzk@...nel.org> wrote:
> >
> > On Sun, Nov 02, 2025 at 08:27:14PM +0000, Peter Griffin wrote:
> > > Each CMU (with the exception of cmu_top) has a corresponding sysreg bank
> > > that contains the BUSCOMPONENT_DRCG_EN and MEMCLK registers.
> > >
> > > If present these registers need to be initialised
> >
> >
> > ... for what exactly? What would happen if this was not initialized?
> 
> The BUSCOMPONENT_DRCG_EN register enables dynamic root clock gating of
> bus components. So it is related to the automatic clock gating feature
> that is being enabled in this series. Things still work without
> initializing this register, but the bus components won't be
> automatically clock gated leading to increased dynamic power
> consumption. Similarly the memclk register enables/disables sram clock
> gate. Up until now we've not been initializing the registers as
> everything from Linux PoV has been in manual clock gating mode and
> until starting to implement this I wasn't aware there were some clock
> related registers in the corresponding sysreg. Additionally with
> Andre's work enabling power domains it has become clear we should be
> saving/restoring these two sysreg clock registers when the power
> domain is turned off and on.
> 
> > What is the exact justification for ABI break - wasn't this working
> > before? Or new feature will not work (thus no ABI break allowed)?
> 
> No, automatic clocks and dynamic root clock gating were not working
> prior to this series. Currently power domains and system wide
> suspend/resume aren't enabled upstream either. As we work on enabling
> these features we are finding some things that in an ideal world we
> would have known about earlier. Unfortunately it's not so obvious just
> from studying the downstream code either as they rely heavily on
> CAL-IF layer that has peeks/pokes all over the memory map especially
> for power/clock related functionality.
> 
> Whilst it is technically an ABI break, I've tried to implement it in a
> backwards compatible way (i.e. an old DT without the samsung,sysreg
> phandle specified) will just fallback to the current behavior of not
> initializing these registers. Things will still work to the extent
> they did prior to this series. With a new DT the registers will be
> initialized, and dynamic power consumption will be better.

So explain that this is needed for proper and complete power management
solution on this SoC, however that is not an ABI break because Linux
driver will be stil backwards compatible.


Best regards,
Krzysztof

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