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Message-ID: <20251104093932.3838876-1-shubhrajyoti.datta@amd.com>
Date: Tue, 4 Nov 2025 15:09:20 +0530
From: Shubhrajyoti Datta <shubhrajyoti.datta@....com>
To: <linux-kernel@...r.kernel.org>, <linux-edac@...r.kernel.org>
CC: <shubhrajyoti.datta@...il.com>, Borislav Petkov <bp@...en8.de>, Tony Luck
<tony.luck@...el.com>, James Morse <james.morse@....com>, "Mauro Carvalho
Chehab" <mchehab@...nel.org>, Robert Richter <rric@...nel.org>, "Shubhrajyoti
Datta" <shubhrajyoti.datta@....com>
Subject: [PATCH v2] EDAC/versalnet: Refactor memory controller initialization and cleanup
Simplify the initialization and cleanup flow for Versal Net DDRMC
controllers in the EDAC driver.
Introduce `init_single_versalnet()` for per-controller setup and
`init_versalnet()` for looping through NUM_CONTROLLERS, also add
rollback logic to handle partial init failures.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@....com>
---
Changes in v2:
- Rename init_single_versalnet() to init_mc() for clarity.
- Rename remove_single_versalnet() to remove_mc() to match naming convention.
- Simplify error handling in init_versalnet() by replacing goto with a rollback loop.
- Reduce indentation and consolidate cleanup logic.
drivers/edac/versalnet_edac.c | 156 ++++++++++++++++++----------------
1 file changed, 83 insertions(+), 73 deletions(-)
diff --git a/drivers/edac/versalnet_edac.c b/drivers/edac/versalnet_edac.c
index 1ded4c3f0213..01edc7408a5c 100644
--- a/drivers/edac/versalnet_edac.c
+++ b/drivers/edac/versalnet_edac.c
@@ -758,7 +758,17 @@ static void versal_edac_release(struct device *dev)
kfree(dev);
}
-static int init_versalnet(struct mc_priv *priv, struct platform_device *pdev)
+static void remove_mc(struct mc_priv *priv, int i)
+{
+ struct mem_ctl_info *mci;
+
+ mci = priv->mci[i];
+ device_unregister(mci->pdev);
+ edac_mc_del_mc(mci->pdev);
+ edac_mc_free(mci);
+}
+
+static int init_mc(struct mc_priv *priv, struct platform_device *pdev, int i)
{
u32 num_chans, rank, dwidth, config;
struct edac_mc_layer layers[2];
@@ -766,87 +776,90 @@ static int init_versalnet(struct mc_priv *priv, struct platform_device *pdev)
struct device *dev;
enum dev_type dt;
char *name;
- int rc, i;
-
- for (i = 0; i < NUM_CONTROLLERS; i++) {
- config = priv->adec[CONF + i * ADEC_NUM];
- num_chans = FIELD_GET(MC5_NUM_CHANS_MASK, config);
- rank = 1 << FIELD_GET(MC5_RANK_MASK, config);
- dwidth = FIELD_GET(MC5_BUS_WIDTH_MASK, config);
-
- switch (dwidth) {
- case XDDR5_BUS_WIDTH_16:
- dt = DEV_X16;
- break;
- case XDDR5_BUS_WIDTH_32:
- dt = DEV_X32;
- break;
- case XDDR5_BUS_WIDTH_64:
- dt = DEV_X64;
- break;
- default:
- dt = DEV_UNKNOWN;
- }
+ int rc;
- if (dt == DEV_UNKNOWN)
- continue;
+ config = priv->adec[CONF + i * ADEC_NUM];
+ num_chans = FIELD_GET(MC5_NUM_CHANS_MASK, config);
+ rank = 1 << FIELD_GET(MC5_RANK_MASK, config);
+ dwidth = FIELD_GET(MC5_BUS_WIDTH_MASK, config);
+
+ switch (dwidth) {
+ case XDDR5_BUS_WIDTH_16:
+ dt = DEV_X16;
+ break;
+ case XDDR5_BUS_WIDTH_32:
+ dt = DEV_X32;
+ break;
+ case XDDR5_BUS_WIDTH_64:
+ dt = DEV_X64;
+ break;
+ default:
+ dt = DEV_UNKNOWN;
+ }
- /* Find the first enabled device and register that one. */
- layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
- layers[0].size = rank;
- layers[0].is_virt_csrow = true;
- layers[1].type = EDAC_MC_LAYER_CHANNEL;
- layers[1].size = num_chans;
- layers[1].is_virt_csrow = false;
+ if (dt == DEV_UNKNOWN)
+ return 0;
- rc = -ENOMEM;
- mci = edac_mc_alloc(i, ARRAY_SIZE(layers), layers,
- sizeof(struct mc_priv));
- if (!mci) {
- edac_printk(KERN_ERR, EDAC_MC, "Failed memory allocation for MC%d\n", i);
- goto err_alloc;
- }
+ /* Find the first enabled device and register that one. */
+ layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
+ layers[0].size = rank;
+ layers[0].is_virt_csrow = true;
+ layers[1].type = EDAC_MC_LAYER_CHANNEL;
+ layers[1].size = num_chans;
+ layers[1].is_virt_csrow = false;
+
+ rc = -ENOMEM;
+ mci = edac_mc_alloc(i, ARRAY_SIZE(layers), layers,
+ sizeof(struct mc_priv));
+ if (!mci) {
+ edac_printk(KERN_ERR, EDAC_MC, "Failed memory allocation for MC%d\n", i);
+ return rc;
+ }
+ priv->mci[i] = mci;
+ priv->dwidth = dt;
+
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ if (!dev)
+ goto err_mc_free;
+ dev->release = versal_edac_release;
+ name = kmalloc(32, GFP_KERNEL);
+ sprintf(name, "versal-net-ddrmc5-edac-%d", i);
+ dev->init_name = name;
+ rc = device_register(dev);
+ if (rc)
+ goto err_mc_free;
- priv->mci[i] = mci;
- priv->dwidth = dt;
+ mci->pdev = dev;
- dev = kzalloc(sizeof(*dev), GFP_KERNEL);
- dev->release = versal_edac_release;
- name = kmalloc(32, GFP_KERNEL);
- sprintf(name, "versal-net-ddrmc5-edac-%d", i);
- dev->init_name = name;
- rc = device_register(dev);
- if (rc)
- goto err_alloc;
+ platform_set_drvdata(pdev, priv);
- mci->pdev = dev;
+ mc_init(mci, dev);
+ rc = edac_mc_add_mc(mci);
+ if (rc) {
+ edac_printk(KERN_ERR, EDAC_MC, "Failed to register MC%d with EDAC core\n", i);
+ goto err_unreg;
+ }
+ return 0;
+err_unreg:
+ device_unregister(mci->pdev);
+err_mc_free:
+ edac_mc_free(mci);
+ return rc;
+}
- platform_set_drvdata(pdev, priv);
+static int init_versalnet(struct mc_priv *priv, struct platform_device *pdev)
+{
+ int rc, i;
- mc_init(mci, dev);
- rc = edac_mc_add_mc(mci);
+ for (i = 0; i < NUM_CONTROLLERS; i++) {
+ rc = init_mc(priv, pdev, i);
if (rc) {
- edac_printk(KERN_ERR, EDAC_MC, "Failed to register MC%d with EDAC core\n", i);
- goto err_alloc;
+ while (i--)
+ remove_mc(priv, i);
+ return rc;
}
}
return 0;
-
-err_alloc:
- while (i--) {
- mci = priv->mci[i];
- if (!mci)
- continue;
-
- if (mci->pdev) {
- device_unregister(mci->pdev);
- edac_mc_del_mc(mci->pdev);
- }
-
- edac_mc_free(mci);
- }
-
- return rc;
}
static void remove_versalnet(struct mc_priv *priv)
@@ -857,9 +870,6 @@ static void remove_versalnet(struct mc_priv *priv)
for (i = 0; i < NUM_CONTROLLERS; i++) {
device_unregister(priv->mci[i]->pdev);
mci = edac_mc_del_mc(priv->mci[i]->pdev);
- if (!mci)
- return;
-
edac_mc_free(mci);
}
}
--
2.34.1
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