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Message-ID: <20251104-iciness-ranting-29dd93fe6a7e@wendy>
Date: Tue, 4 Nov 2025 13:18:09 +0000
From: Conor Dooley <conor.dooley@...rochip.com>
To: Aleksa Paunovic <aleksa.paunovic@...cgroup.com>
CC: "conor@...nel.org" <conor@...nel.org>, "alex@...ti.fr" <alex@...ti.fr>,
"aou@...s.berkeley.edu" <aou@...s.berkeley.edu>, "cfu@...ecomp.com"
<cfu@...ecomp.com>, Djordje Todorovic <Djordje.Todorovic@...cgroup.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
"palmer@...belt.com" <palmer@...belt.com>, "pjw@...nel.org" <pjw@...nel.org>
Subject: Re: [PATCH] riscv: Update MIPS vendor id to 0x127.
On Tue, Nov 04, 2025 at 11:53:49AM +0000, Aleksa Paunovic wrote:
> On 11/3/25 23:07, Conor Dooley wrote:
> > On Mon, Nov 03, 2025 at 04:05:48PM +0100, Aleksa Paunovic wrote:
> >> From: Chao-ying Fu <cfu@...ecomp.com>
> >>
> >> [1] defines MIPS vendor id as 0x127.
> >>
> >> [1] https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
> >>
> >> Fixes: a8fed1bc03ace27902338e4f0d318335883ac847 ("riscv: Add xmipsexectl as a vendor extension")
> > Incorrect format for fixes tags!
>
> Will fix that in v2.
>
> >
> >> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@...cgroup.com>
> >> ---
> >> arch/riscv/include/asm/vendorid_list.h | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
> >> index 3b09874d7a6dfb8f8aa45b0be41c20711d539e78..55205f7938055ba2b744dba5118bba935bcac008 100644
> >> --- a/arch/riscv/include/asm/vendorid_list.h
> >> +++ b/arch/riscv/include/asm/vendorid_list.h
> >> @@ -9,6 +9,6 @@
> >> #define MICROCHIP_VENDOR_ID 0x029
> >> #define SIFIVE_VENDOR_ID 0x489
> >> #define THEAD_VENDOR_ID 0x5b7
> >> -#define MIPS_VENDOR_ID 0x722
> >> +#define MIPS_VENDOR_ID 0x127
> > How was this ever wrong? Do devices exist with this old ID? Do we need
> > to support both as vendor IDs for MIPS?
>
> I'm not sure how it first started, but since we worked on qemu as well, we never noticed any issues while testing.
> It shouldn't cause any problems in the future though.
So all the hardware uses the 0x127 id? Where did 0x722 come from?
I recall qemu defaults to 0x0, so were none of the mips code paths
tested, or were they tested with a qemu modified to use 0x722?
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