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Message-ID: <9ad5a25e-04b6-48b6-b1e0-b9f51e49f8e6@163.com>
Date: Wed, 5 Nov 2025 23:56:15 +0800
From: Hans Zhang <18255117159@....com>
To: bhelgaas@...gle.com, helgaas@...nel.org, linux-pci@...r.kernel.org,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 1/4] PCI: Add macro for secondary bus reset delay

Hi Bjorn,

I wonder if this is still necessary? If not, please drop it as well. Thanks.

Best regards,
Hans

On 2025/11/2 00:05, Hans Zhang wrote:
> Add PCI_T_RST_SEC_BUS_DELAY_MS macro for the secondary bus reset
> delay value according to PCIe r7.0 spec, section 7.5.1.3.13.
> 
> Signed-off-by: Hans Zhang <18255117159@....com>
> ---
>   drivers/pci/pci.c | 7 ++-----
>   drivers/pci/pci.h | 3 +++
>   2 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index b14dd064006c..86449f2d627b 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -4912,11 +4912,8 @@ void pci_reset_secondary_bus(struct pci_dev *dev)
>   	ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
>   	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
>   
> -	/*
> -	 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms.  Double
> -	 * this to 2ms to ensure that we meet the minimum requirement.
> -	 */
> -	msleep(2);
> +	/* Double this to 2ms to ensure that we meet the minimum requirement */
> +	msleep(2 * PCI_T_RST_SEC_BUS_DELAY_MS);
>   
>   	ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
>   	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index 4492b809094b..31f975619774 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -63,6 +63,9 @@ struct pcie_tlp_log;
>   #define PCIE_LINK_WAIT_MAX_RETRIES	10
>   #define PCIE_LINK_WAIT_SLEEP_MS		90
>   
> +/* PCIe r7.0, sec 7.5.1.3.13, requires minimum Trst of 1ms */
> +#define PCI_T_RST_SEC_BUS_DELAY_MS	1
> +
>   /* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */
>   #define PCIE_MSG_TYPE_R_RC	0
>   #define PCIE_MSG_TYPE_R_ADDR	1


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