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Message-ID: <5b8e13e227dd0e965125bfdb486f1ed665e0d8f1.1762354366.git.tommaso.merciai.xr@bp.renesas.com>
Date: Wed, 5 Nov 2025 16:39:16 +0100
From: Tommaso Merciai <tommaso.merciai.xr@...renesas.com>
To: tomm.merciai@...il.com
Cc: linux-renesas-soc@...r.kernel.org,
biju.das.jz@...renesas.com,
Tommaso Merciai <tommaso.merciai.xr@...renesas.com>,
Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Peter Rosin <peda@...ntia.se>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>,
Arnd Bergmann <arnd@...db.de>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
linux-phy@...ts.infradead.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v2 20/21] arm64: dts: renesas: r9a09g047: Add USB2.0 support
The Renesas RZ/G3E ("R9A09G047") SoC supports 1x channel with OTG/DRD
and 1x channel with host interface.
Add the ECHI, OHCI, USB2.0 PHY and reset control nodes for USB2.0 channels
in R9A09G047 SoC DTSI.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@...renesas.com>
---
v1->v2:
- Added mux-state-cells into usb20phyrst and usb21phyrst
- Use mux-states into usb2_phy0 and usb2_phy1 to mux VBUS_SEL
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 125 +++++++++++++++++++++
1 file changed, 125 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 7a469de3bb62..90435e5673fb 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -853,6 +853,131 @@ gic: interrupt-controller@...00000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+ ohci0: usb@...00000 {
+ compatible = "generic-ohci";
+ reg = <0 0x15800000 0 0x100>;
+ interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>;
+ resets = <&usb20phyrst>, <&cpg 0xac>;
+ phys = <&usb2_phy0 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ohci1: usb@...10000 {
+ compatible = "generic-ohci";
+ reg = <0 0x15810000 0 0x100>;
+ interrupts = <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>;
+ resets = <&usb21phyrst>, <&cpg 0xad>;
+ phys = <&usb2_phy1 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci0: usb@...00100 {
+ compatible = "generic-ehci";
+ reg = <0 0x15800100 0 0x100>;
+ interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>;
+ resets = <&usb20phyrst>, <&cpg 0xac>;
+ phys = <&usb2_phy0 2>;
+ phy-names = "usb";
+ companion = <&ohci0>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci1: usb@...10100 {
+ compatible = "generic-ehci";
+ reg = <0 0x15810100 0 0x100>;
+ interrupts = <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>;
+ resets = <&usb21phyrst>, <&cpg 0xad>;
+ phys = <&usb2_phy1 2>;
+ phy-names = "usb";
+ companion = <&ohci1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy0: usb-phy@...00200 {
+ compatible = "renesas,usb2-phy-r9a09g047",
+ "renesas,usb2-phy-r9a09g057";
+ reg = <0 0x15800200 0 0x700>;
+ interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb3>,
+ <&cpg CPG_CORE R9A09G047_USB2_0_CLK_CORE0>;
+ clock-names = "fck", "usb_x1";
+ resets = <&usb20phyrst>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ mux-states = <&usb20phyrst 1>;
+ status = "disabled";
+
+ usb2_phy0_vbus_otg: vbus-regulator {
+ regulator-name = "USB2PHY0-VBUS-OTG";
+ status = "disabled";
+ };
+ };
+
+ usb2_phy1: usb-phy@...10200 {
+ compatible = "renesas,usb2-phy-r9a09g047",
+ "renesas,usb2-phy-r9a09g057";
+ reg = <0 0x15810200 0 0x700>;
+ interrupts = <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb4>,
+ <&cpg CPG_CORE R9A09G047_USB2_0_CLK_CORE1>;
+ clock-names = "fck", "usb_x1";
+ resets = <&usb21phyrst>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ mux-states = <&usb21phyrst 0>;
+ status = "disabled";
+ };
+
+ hsusb: usb@...20000 {
+ compatible = "renesas,usbhs-r9a09g047",
+ "renesas,rzg2l-usbhs";
+ reg = <0 0x15820000 0 0x10000>;
+ interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>;
+ resets = <&usb20phyrst>, <&cpg 0xae>;
+ phys = <&usb2_phy0 3>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb20phyrst: reset-controller@...30000 {
+ compatible = "renesas,r9a09g047-usb2phy-reset",
+ "renesas,r9a09g057-usb2phy-reset";
+ reg = <0 0x15830000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xb6>;
+ resets = <&cpg 0xaf>;
+ power-domains = <&cpg>;
+ #reset-cells = <0>;
+ #mux-state-cells = <1>;
+ status = "disabled";
+ };
+
+ usb21phyrst: reset-controller@...40000 {
+ compatible = "renesas,r9a09g047-usb2phy-reset",
+ "renesas,r9a09g057-usb2phy-reset";
+ reg = <0 0x15840000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xb7>;
+ resets = <&cpg 0xaf>;
+ power-domains = <&cpg>;
+ #reset-cells = <0>;
+ #mux-state-cells = <1>;
+ status = "disabled";
+ };
+
sdhi0: mmc@...00000 {
compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057";
reg = <0x0 0x15c00000 0 0x10000>;
--
2.43.0
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