linux-kernel - Re: [PATCH 3/4 v3] PCI: s32g: Add initial PCIe support (RC)

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Message-ID: <bf3b2d2a-ce3e-87af-4154-abd022c6a3b4@linux.intel.com>
Date: Wed, 5 Nov 2025 12:43:09 +0200 (EET)
From: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
To: Niklas Cassel <cassel@...nel.org>
cc: Vincent Guittot <vincent.guittot@...aro.org>, 
    Bjorn Helgaas <helgaas@...nel.org>, chester62515@...il.com, 
    mbrugger@...e.com, ghennadi.procopciuc@....nxp.com, s32@....com, 
    bhelgaas@...gle.com, jingoohan1@...il.com, lpieralisi@...nel.org, 
    kwilczynski@...nel.org, mani@...nel.org, robh@...nel.org, 
    krzk+dt@...nel.org, conor+dt@...nel.org, Ionut.Vicovan@....com, 
    larisa.grigore@....com, Ghennadi.Procopciuc@....com, 
    ciprianmarian.costea@....com, bogdan.hamciuc@....com, Frank.li@....com, 
    linux-arm-kernel@...ts.infradead.org, linux-pci@...r.kernel.org, 
    devicetree@...r.kernel.org, LKML <linux-kernel@...r.kernel.org>, 
    imx@...ts.linux.dev
Subject: Re: [PATCH 3/4 v3] PCI: s32g: Add initial PCIe support (RC)

On Wed, 5 Nov 2025, Niklas Cassel wrote:

> On Fri, Oct 24, 2025 at 08:50:46AM +0200, Vincent Guittot wrote:
> > On Wed, 22 Oct 2025 at 21:04, Bjorn Helgaas <helgaas@...nel.org> wrote:
> > > > +     dw_pcie_dbi_ro_wr_en(pci);
> > > > +
> > > > +     val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE);
> > > > +     val |= PORT_FORCE_DO_DESKEW_FOR_SRIS;
> > > > +     dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val);
> > > > +
> > > > +     /*
> > > > +      * Set max payload supported, 256 bytes and
> > > > +      * relaxed ordering.
> > > > +      */
> > > > +     val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
> > > > +     val &= ~(PCI_EXP_DEVCTL_RELAX_EN |
> > > > +              PCI_EXP_DEVCTL_PAYLOAD |
> > > > +              PCI_EXP_DEVCTL_READRQ);
> > > > +     val |= PCI_EXP_DEVCTL_RELAX_EN |
> > > > +            PCI_EXP_DEVCTL_PAYLOAD_256B |
> > > > +            PCI_EXP_DEVCTL_READRQ_256B;
> > > > +     dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
> > >
> > > MPS and relaxed ordering should be configured by the PCI core.  Is
> > > there some s32g-specific restriction about these?
> > 
> > I will check with the team why they did that
> 
> Most likely, the reason is that, the PCI core does not set the MPS to the
> maximum supported MPS for the root port.

PCI core set/doesn't set MPS based on config. Perhaps try with 
CONFIG_PCIE_BUS_PERFORMANCE.

> So without that change, the port will use use 128B instead of 256B.
> 
> I assume that you should be able to drop (at least the MPS part) if this
> change gets accepted:
> https://lore.kernel.org/linux-pci/20251104165125.174168-1-18255117159@163.com/
> 
> 
> Kind regards,
> Niklas
> 

-- 
 i.