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Message-Id: <20251106-add_l3_routing-v1-2-dcbb8368ca54@renesas.com>
Date: Thu, 06 Nov 2025 13:55:26 +0100
From: Michael Dege <michael.dege@...esas.com>
To: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>, 
 Andrew Lunn <andrew+netdev@...n.ch>, 
 "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, 
 Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, 
 Richard Cochran <richardcochran@...il.com>, 
 Niklas Söderlund <niklas.soderlund@...natech.se>, 
 Paul Barker <paul@...rker.dev>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, 
 Geert Uytterhoeven <geert+renesas@...der.be>, 
 Magnus Damm <magnus.damm@...il.com>
Cc: netdev@...r.kernel.org, linux-renesas-soc@...r.kernel.org, 
 linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, 
 Nikita Yushchenko <nikita.yoush@...entembedded.com>, 
 Christophe JAILLET <christophe.jaillet@...adoo.fr>, 
 Michael Dege <michael.dege@...esas.com>
Subject: [PATCH net-next 02/10] net: renesas: rswitch: enable Phy link
 status pin

Enable Phy link status pin for boards which support this feature.

Signed-off-by: Michael Dege <michael.dege@...esas.com>
---
 drivers/net/ethernet/renesas/rswitch.h      |  1 +
 drivers/net/ethernet/renesas/rswitch_main.c | 12 ++++++++++--
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/renesas/rswitch.h b/drivers/net/ethernet/renesas/rswitch.h
index 8168c4cc83fe..a65ba10ae435 100644
--- a/drivers/net/ethernet/renesas/rswitch.h
+++ b/drivers/net/ethernet/renesas/rswitch.h
@@ -960,6 +960,7 @@ struct rswitch_etha {
 	u8 mac_addr[MAX_ADDR_LEN];
 	int link;
 	int speed;
+	bool link_pin;
 
 	/* This hardware could not be initialized twice so that marked
 	 * this flag to avoid multiple initialization.
diff --git a/drivers/net/ethernet/renesas/rswitch_main.c b/drivers/net/ethernet/renesas/rswitch_main.c
index 8d8acc2124b8..dd9a0e7a9d74 100644
--- a/drivers/net/ethernet/renesas/rswitch_main.c
+++ b/drivers/net/ethernet/renesas/rswitch_main.c
@@ -1192,9 +1192,15 @@ static void rswitch_rmac_setting(struct rswitch_etha *etha, const u8 *mac)
 
 static void rswitch_etha_enable_mii(struct rswitch_etha *etha)
 {
-	rswitch_modify(etha->addr, MPIC, MPIC_PSMCS | MPIC_PSMHT,
+	/* PSMCT: PHY station Management capture adjustment in clk cycles */
+	/* PSMHT: PHY Station Management Hold Time adjustment in clk cycles */
+	/* PSMCS: PHY Station Management Clock selection (clk divider) */
+	/* PLSPP: PHY Link Status Pin Plugged */
+
+	rswitch_modify(etha->addr, MPIC, MPIC_PSMCS | MPIC_PSMHT | MPIC_PLSPP,
 		       FIELD_PREP(MPIC_PSMCS, etha->psmcs) |
-		       FIELD_PREP(MPIC_PSMHT, 0x06));
+		       FIELD_PREP(MPIC_PSMHT, 0x06) |
+		       FIELD_PREP(MPIC_PLSPP, etha->link_pin));
 }
 
 static int rswitch_etha_hw_init(struct rswitch_etha *etha, const u8 *mac)
@@ -1338,6 +1344,8 @@ static int rswitch_etha_get_params(struct rswitch_device *rdev)
 	if (err)
 		return err;
 
+	rdev->etha->link_pin = of_property_read_bool(rdev->np_port, "link-pin");
+
 	err = of_property_read_u32(rdev->np_port, "max-speed", &max_speed);
 	if (!err) {
 		rdev->etha->speed = max_speed;

-- 
2.43.0


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