linux-kernel - [PATCH net-next 01/10] net: renesas: rswitch: cleanup MII settings

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Message-Id: <20251106-add_l3_routing-v1-1-dcbb8368ca54@renesas.com>
Date: Thu, 06 Nov 2025 13:55:25 +0100
From: Michael Dege <michael.dege@...esas.com>
To: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>, 
 Andrew Lunn <andrew+netdev@...n.ch>, 
 "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, 
 Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, 
 Richard Cochran <richardcochran@...il.com>, 
 Niklas Söderlund <niklas.soderlund@...natech.se>, 
 Paul Barker <paul@...rker.dev>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, 
 Geert Uytterhoeven <geert+renesas@...der.be>, 
 Magnus Damm <magnus.damm@...il.com>
Cc: netdev@...r.kernel.org, linux-renesas-soc@...r.kernel.org, 
 linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, 
 Nikita Yushchenko <nikita.yoush@...entembedded.com>, 
 Christophe JAILLET <christophe.jaillet@...adoo.fr>, 
 Michael Dege <michael.dege@...esas.com>
Subject: [PATCH net-next 01/10] net: renesas: rswitch: cleanup MII settings

Add Phy interface modes and link speeds.

Signed-off-by: Michael Dege <michael.dege@...esas.com>
---
 drivers/net/ethernet/renesas/rswitch.h | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/renesas/rswitch.h b/drivers/net/ethernet/renesas/rswitch.h
index a1d4a877e5bd..8168c4cc83fe 100644
--- a/drivers/net/ethernet/renesas/rswitch.h
+++ b/drivers/net/ethernet/renesas/rswitch.h
@@ -732,15 +732,26 @@ enum rswitch_etha_mode {
 #define EAVCC_VEM_SC_TAG	(0x3 << 16)

 #define MPIC_PIS		GENMASK(2, 0)
-#define MPIC_PIS_GMII		2
-#define MPIC_PIS_XGMII		4
 #define MPIC_LSC		GENMASK(5, 3)
-#define MPIC_LSC_100M		1
-#define MPIC_LSC_1G		2
-#define MPIC_LSC_2_5G		3
+#define MPIC_PLSPP		BIT(10)
 #define MPIC_PSMCS		GENMASK(22, 16)
 #define MPIC_PSMHT		GENMASK(26, 24)

+enum phy_if_select {
+	MPIC_PIS_MII   =        0,
+	MPIC_PIS_GMII  =        2,
+	MPIC_PIS_XGMII =        4,
+};
+
+enum link_speed_conf {
+	MPIC_LSC_10M,
+	MPIC_LSC_100M,
+	MPIC_LSC_1G,
+	MPIC_LSC_2_5G,
+	MPIC_LSC_5G,
+	MPIC_LSC_10G,
+};
+
 #define MPSM_PSME		BIT(0)
 #define MPSM_MFF		BIT(2)
 #define MPSM_MMF_C22		0

-- 
2.43.0