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Message-ID: <20251106141227.899054-6-s-jain1@ti.com>
Date: Thu, 6 Nov 2025 19:42:27 +0530
From: Swamil Jain <s-jain1@...com>
To: <jyri.sarha@....fi>, <tomi.valkeinen@...asonboard.com>,
<maarten.lankhorst@...ux.intel.com>, <mripard@...nel.org>,
<tzimmermann@...e.de>, <airlied@...il.com>, <simona@...ll.ch>, <nm@...com>,
<vigneshr@...com>, <kristo@...nel.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>, <lee@...nel.org>,
<louis.chauvet@...tlin.com>, <aradhya.bhatia@...ux.dev>
CC: <devarsht@...com>, <praneeth@...com>, <h-shenoy@...com>,
<dri-devel@...ts.freedesktop.org>, <linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: [RESEND PATCH v2 5/5] drm/tidss: Fix sampling edge configuration
From: Louis Chauvet <louis.chauvet@...tlin.com>
As stated in the AM62x Technical Reference Manual (SPRUIV7B)[1], the data
sampling edge needs to be configured in two distinct registers: one in the
TIDSS IP and another in the memory-mapped control register modules. Since
the latter is not within the same address range, a phandle to a syscon
device is used to access the regmap.
Configure the CTRL_MMR register, as mentioned in the Technical Reference
Manual to fix sampling edge.
[1]: https://www.ti.com/lit/ug/spruiv7b/spruiv7b.pdf
Fixes: ad2ac9dc9426 ("drm/tidss: Add support for AM625 DSS")
Fixes: 5cc5ea7b6d7b ("drm/tidss: Add support for AM62A7 DSS")
Cc: stable@...r.kernel.org
Signed-off-by: Louis Chauvet <louis.chauvet@...tlin.com>
Signed-off-by: Swamil Jain <s-jain1@...com>
---
drivers/gpu/drm/tidss/tidss_dispc.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
index d8e1a1bcd660..d09eecb72dc0 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -500,6 +500,7 @@ struct dispc_device {
const struct dispc_features *feat;
struct clk *fclk;
+ struct regmap *clk_ctrl;
bool is_enabled;
@@ -1234,6 +1235,11 @@ void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
mode->crtc_hdisplay - 1) |
FIELD_PREP(DISPC_VP_SIZE_SCREEN_VDISPLAY_MASK,
mode->crtc_vdisplay - 1));
+
+ if (dispc->clk_ctrl) {
+ regmap_update_bits(dispc->clk_ctrl, 0, 0x100, ipc ? 0x100 : 0x000);
+ regmap_update_bits(dispc->clk_ctrl, 0, 0x200, rf ? 0x200 : 0x000);
+ }
}
void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport)
@@ -3003,6 +3009,14 @@ int dispc_init(struct tidss_device *tidss)
dispc_init_errata(dispc);
+ dispc->clk_ctrl = syscon_regmap_lookup_by_phandle_optional(tidss->dev->of_node,
+ "ti,clk-ctrl");
+ if (IS_ERR(dispc->clk_ctrl)) {
+ r = dev_err_probe(dispc->dev, PTR_ERR(dispc->clk_ctrl),
+ "DISPC: syscon_regmap_lookup_by_phandle failed.\n");
+ return r;
+ }
+
dispc->fourccs = devm_kcalloc(dev, ARRAY_SIZE(dispc_color_formats),
sizeof(*dispc->fourccs), GFP_KERNEL);
if (!dispc->fourccs)
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