linux-kernel - Re: [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90

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Message-ID: <20251106-tinfoil-primer-30ff181203f4@spud>
Date: Thu, 6 Nov 2025 17:10:38 +0000
From: Conor Dooley <conor@...nel.org>
To: Junhui Liu <junhui.liu@...moral.tech>, tglx@...utronix.de
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, Paul Walmsley <pjw@...nel.org>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>,
	Thomas Gleixner <tglx@...utronix.de>,
	Samuel Holland <samuel.holland@...ive.com>,
	Chen Wang <unicorn_wang@...look.com>,
	Inochi Amaoto <inochiama@...il.com>,
	Daniel Lezcano <daniel.lezcano@...aro.org>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	Jiri Slaby <jirislaby@...nel.org>, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...ive.com>, linux-riscv@...ts.infradead.org,
	Inochi Amaoto <inochiama@...look.com>, sophgo@...ts.linux.dev,
	linux-serial@...r.kernel.org,
	Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
	Conor Dooley <conor.dooley@...rochip.com>
Subject: Re: [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90

Thomas,

On Tue, Oct 28, 2025 at 07:39:07PM +0000, Conor Dooley wrote:
> Thomas, Junhui,
> 
> On Tue, Oct 21, 2025 at 05:41:35PM +0800, Junhui Liu wrote:
> > This introduces initial support for the Anlogic DR1V90 SoC [1] and the
> > Milianke MLKPAI-FS01 [2] board.
> > 
> > The DR1V90 is a RISC-V based FPSoC from Anlogic, featuring a Nuclei
> > UX900 [3] core as its processing system (PS) and 94,464 LUTs in the
> > programmable logic (PL) part. The Milianke MLKPAI-FS01 board is one of
> > the first platforms based on this SoC, with UART1 routed to a Type-C
> > interface for console access.
> > 
> > Tested on the Milianke MLKPAI-FS01 board with both the vendor's OpenSBI
> > and the not-yet-upstreamed mainline OpenSBI [4], as well as the vendor’s
> > U-Boot. Because the vendor’s OpenSBI is loaded at 0x1f300000, we have
> > to additionally reserve the DRAM region 0x1fe00000–0x1fffffff to prevent
> > overlap if using vendor's OpenSBI.
> > 
> > Link: https://www.anlogic.com/product/fpga/saldragon/dr1 [1]
> > Link: https://www.milianke.com/product-item-104.html [2]
> > Link: https://nucleisys.com/product/900.php [3]
> > Link: https://github.com/pigmoral/opensbi/tree/dr1v90 [4]
> > ---
> > Changes in v3:
> > - Update DT binding to use ACLINT instead of CLINT
> > - Drop MAINTAINERS patch
> > - Rebase on v6.18-rc1
> > - Link to v2: https://lore.kernel.org/r/20250922-dr1v90-basic-dt-v2-0-64d28500cb37@pigmoral.tech
> > 
> > Changes in v2:
> > - Add MAINTAINERS entry for the DR1V90 platform
> > - Remove the riscv,isa property of cpu and reorder propertyies
> > - Fix clint base address in the dtsi
> > - Change the memory node to cover the full 512MB RAM in board dts
> > - Link to v1: https://lore.kernel.org/r/20250721-dr1v90-basic-dt-v1-0-5740c5199c47@pigmoral.tech
> > 
> > ---
> > Junhui Liu (13):
> >       dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei
> >       dt-bindings: riscv: Add Nuclei UX900 compatibles
> >       dt-bindings: riscv: Add Anlogic DR1V90
> >       dt-bindings: interrupt-controller: Add Anlogic DR1V90 PLIC
> >       dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI
> >       dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT SSWI
> >       dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER
> >       dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart
> >       irqchip/aclint-sswi: Add Nuclei UX900 support
> 
> I'm happy enough with this series to grab it, but while I don't mind
> taking some trivial binding changes with it, I don't want to take an
> irqchip driver patch. Would you be able to apply the irqchip stuff
> Thomas?


Could you pick up 4-6 and 9 here please?

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