linux-kernel - Re: [PATCH 1/4 v3] dt-bindings: PCI: s32g: Add NXP PCIe controller

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Message-ID: <20251106173853.GA1959661@bhelgaas>
Date: Thu, 6 Nov 2025 11:38:53 -0600
From: Bjorn Helgaas <helgaas@...nel.org>
To: Vincent Guittot <vincent.guittot@...aro.org>
Cc: Manivannan Sadhasivam <mani@...nel.org>, chester62515@...il.com,
	mbrugger@...e.com, ghennadi.procopciuc@....nxp.com, s32@....com,
	bhelgaas@...gle.com, jingoohan1@...il.com, lpieralisi@...nel.org,
	kwilczynski@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
	conor+dt@...nel.org, Ionut.Vicovan@....com, larisa.grigore@....com,
	Ghennadi.Procopciuc@....com, ciprianmarian.costea@....com,
	bogdan.hamciuc@....com, Frank.li@....com,
	linux-arm-kernel@...ts.infradead.org, linux-pci@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	imx@...ts.linux.dev, cassel@...nel.org,
	Senchuan Zhang <zhangsenchuan@...incomputing.com>
Subject: Re: [PATCH 1/4 v3] dt-bindings: PCI: s32g: Add NXP PCIe controller

[+cc Senchuan]

On Thu, Nov 06, 2025 at 09:09:01AM +0100, Vincent Guittot wrote:
> On Thu, 6 Nov 2025 at 08:12, Manivannan Sadhasivam <mani@...nel.org> wrote:
> > On Wed, Oct 22, 2025 at 07:43:06PM +0200, Vincent Guittot wrote:
> > > Describe the PCIe host controller available on the S32G platforms.

> > > +            phys = <&serdes0 PHY_TYPE_PCIE 0 0>;
> >
> > PHY is a Root Port specific resource, not Root Complex. So it
> > should be moved to the Root Port node and the controller driver
> > should parse the Root Port node and control PHY. Most of the
> > existing platforms still specify PHY and other Root Port
> > properties in controller node, but they are wrong.
> 
> Yeah, we had similar discussion on v1 and as designware core code
> doesn't support it, the goal was to follow other implementations
> until designware core is able to parse root port nodes.  I can add a
> root port node for the phy and parse it in s32 probe function but
> then If I need to restrict the number of lane to 1 instead of the
> default 2 with num-lanes then I have to put it the controller node
> otherwise designware core node will not get it.

I think it's better to put the PHY info, including num-lanes, in Root
Port DT nodes now even thought the DWC core doesn't explicitly support
that yet because it's much easier to change the DWC core and the
driver code than it is to change the DT structure.

That will mean a little extra code in the s32g driver now, but we will
be able to remove that eventually.  If we leave the PHY in the DT
controller node, we may eventually end up having to support two s32g
DT structures: the single RP style with PHY in the controller, and a
multiple RP style with PHY in the RP.

We'll likely have both structures for many existing drivers, but I
think it will be simpler if new drivers can avoid the old one.

The eic7700 driver is an example of num-lanes support in the driver:
https://lore.kernel.org/linux-pci/20251030083143.1341-1-zhangsenchuan@eswincomputing.com/

Bjorn