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Message-Id: <20251107-qcs615-spin-2-v2-3-a2d7c4fbf6e6@oss.qualcomm.com>
Date: Fri, 07 Nov 2025 02:20:08 +0530
From: Akhil P Oommen <akhilpo@....qualcomm.com>
To: Rob Clark <robin.clark@....qualcomm.com>, Sean Paul <sean@...rly.run>,
Konrad Dybcio <konradybcio@...nel.org>,
Dmitry Baryshkov <lumag@...nel.org>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Jessica Zhang <jesszhan0024@...il.com>
Cc: Dan Carpenter <dan.carpenter@...aro.org>, linux-arm-msm@...r.kernel.org,
dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
Akhil P Oommen <akhilpo@....qualcomm.com>,
Jie Zhang <jie.zhang@....qualcomm.com>
Subject: [PATCH v2 3/6] dt-bindings: display/msm/rgmu: Document A612 RGMU
From: Jie Zhang <jie.zhang@....qualcomm.com>
RGMU a.k.a Reduced Graphics Management Unit is a small state machine
with the sole purpose of providing IFPC (Inter Frame Power Collapse)
support. Compared to GMU, it doesn't manage GPU clock, voltage
scaling, bw voting or any other functionalities. All it does is detect
an idle GPU and toggle the GDSC switch. As it doesn't access DDR space,
it doesn't require iommu.
So far, only Adreno 612 GPU has an RGMU core. Document RGMU in the GMU's
schema.
Signed-off-by: Jie Zhang <jie.zhang@....qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@....qualcomm.com>
---
.../devicetree/bindings/display/msm/rgmu.yaml | 131 +++++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 132 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/rgmu.yaml b/Documentation/devicetree/bindings/display/msm/rgmu.yaml
new file mode 100644
index 000000000000..7621556477d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/rgmu.yaml
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/display/msm/rgmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RGMU attached to certain Adreno GPUs
+
+maintainers:
+ - Rob Clark <robin.clark@....qualcomm.com>
+
+description: |
+ RGMU (Reduced Graphics Management Unit) IP is present in some GPUs that
+ belong to Adreno A6xx family. It is a small state machine that helps to
+ toggle the GX GDSC (connected to CX rail) to implement IFPC feature and save
+ power.
+
+properties:
+ compatible:
+ items:
+ - const: qcom,adreno-rgmu-612.0
+ - const: qcom,adreno-rgmu
+
+ reg:
+ items:
+ - description: Core RGMU registers
+
+ reg-names:
+ items:
+ - const: gmu
+
+ clocks:
+ items:
+ - description: GMU clock
+ - description: GPU CX clock
+ - description: GPU AXI clock
+ - description: GPU MEMNOC clock
+ - description: GPU SMMU vote clock
+
+ clock-names:
+ items:
+ - const: gmu
+ - const: cxo
+ - const: axi
+ - const: memnoc
+ - const: smmu_vote
+
+ power-domains:
+ items:
+ - description: CX GDSC power domain
+ - description: GX GDSC power domain
+
+ power-domain-names:
+ items:
+ - const: cx
+ - const: gx
+
+ interrupts:
+ items:
+ - description: GMU OOB interrupt
+ - description: GMU interrupt
+
+ interrupt-names:
+ items:
+ - const: oob
+ - const: gmu
+
+ operating-points-v2: true
+ opp-table:
+ type: object
+
+required:
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - power-domains
+ - power-domain-names
+ - interrupts
+ - interrupt-names
+ - operating-points-v2
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,qcs615-gpucc.h>
+ #include <dt-bindings/clock/qcom,qcs615-gcc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ rgmu: rgmu@...a000 {
+ compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu";
+
+ reg = <0x05000000 0x90000>;
+ reg-names = "gmu";
+
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+ clock-names = "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "smmu_vote";
+
+ power-domains = <&gpucc CX_GDSC>,
+ <&gpucc GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "oob",
+ "gmu";
+
+ operating-points-v2 = <&rgmu_opp_table>;
+
+ rgmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index ea854fa44b20..c75911e70c82 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7895,6 +7895,7 @@ S: Maintained
B: https://gitlab.freedesktop.org/drm/msm/-/issues
T: git https://gitlab.freedesktop.org/drm/msm.git
F: Documentation/devicetree/bindings/display/msm/gpu.yaml
+F: Documentation/devicetree/bindings/display/msm/rgmu.yaml
F: Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml
F: drivers/gpu/drm/msm/adreno/
F: drivers/gpu/drm/msm/msm_gpu.*
--
2.51.0
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