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Message-ID: <20251106000053.GA1932421@bhelgaas>
Date: Wed, 5 Nov 2025 18:00:53 -0600
From: Bjorn Helgaas <helgaas@...nel.org>
To: Vincent Guittot <vincent.guittot@...aro.org>
Cc: chester62515@...il.com, mbrugger@...e.com,
	ghennadi.procopciuc@....nxp.com, s32@....com, bhelgaas@...gle.com,
	jingoohan1@...il.com, lpieralisi@...nel.org, kwilczynski@...nel.org,
	mani@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
	conor+dt@...nel.org, Ionut.Vicovan@....com, larisa.grigore@....com,
	Ghennadi.Procopciuc@....com, ciprianmarian.costea@....com,
	bogdan.hamciuc@....com, Frank.li@....com,
	linux-arm-kernel@...ts.infradead.org, linux-pci@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	imx@...ts.linux.dev, cassel@...nel.org
Subject: Re: [PATCH 1/4 v3] dt-bindings: PCI: s32g: Add NXP PCIe controller

On Wed, Oct 22, 2025 at 07:43:06PM +0200, Vincent Guittot wrote:
> Describe the PCIe host controller available on the S32G platforms.

> +            reg = <0x00 0x40400000 0x0 0x00001000>,   /* dbi registers */
> +                  <0x00 0x40420000 0x0 0x00001000>,   /* dbi2 registers */
> +                  <0x00 0x40460000 0x0 0x00001000>,   /* atu registers */
> +                  <0x00 0x40470000 0x0 0x00001000>,   /* dma registers */
> +                  <0x00 0x40481000 0x0 0x000000f8>,   /* ctrl registers */
> +                  <0x5f 0xffffe000 0x0 0x00002000>;  /* config space */

Fix comment alignment.

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