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Message-ID: <3381ef56c1ff34a0b54cf76010889b5523ead825.1762387665.git.khairul.anuar.romli@altera.com>
Date: Fri, 7 Nov 2025 07:35:26 +0800
From: Khairul Anuar Romli <khairul.anuar.romli@...era.com>
To: Dinh Nguyen <dinguyen@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Mahesh Rao <mahesh.rao@...era.com>,
linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org,
Khairul Anuar Romli <khairul.anuar.romli@...era.com>
Subject: [PATCH v6 2/2] arm64: dts: intel: Add Agilex5 SVC node with memory region
Introduce the Stratix10 SoC Service Layer (SVC) node for Agilex5 SoCs. This
node includes the compatible string "intel,agilex5-svc" and references a
reserved memory region used for communication with the Secure Device
Manager (SDM).
Agilex5 introduces changes in how reserved memory is mapped and accessed
compared to previous SoC generations. This commit updates the device tree
structure to support Agilex5-specific handling of the SVC interface.
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@...era.com>
---
Changes in v6:
- Move svc node below cpu node.
Changes in v5:
- No change.
Changes in v4:
- Exclude peers reviewers in the sign off.
Changes in v3:
- include iommu property in svc node.
- Rephrase git commit message to describe iommu presence
in Agilex5
Changes in v2:
- Rephrase commit message to exclude mentioning iommu
---
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 408911ea7bc5..bf7128adddde 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -79,6 +79,15 @@ L3: l3-cache {
};
+ firmware {
+ svc {
+ compatible = "intel,agilex5-svc";
+ method = "smc";
+ memory-region = <&service_reserved>;
+ iommus = <&smmu 10>;
+ };
+ };
+
psci {
compatible = "arm,psci-0.2";
method = "smc";
--
2.43.7
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