lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <tecoemfjvcuwrvhiqxla2e7b27tgsmkahrbe2msr6vlh65alvp@vhlklrfasjd5>
Date: Thu, 6 Nov 2025 11:51:00 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
Cc: Bjorn Helgaas <helgaas@...nel.org>, 
	Lorenzo Pieralisi <lpieralisi@...nel.org>, Krzysztof Wilczyński <kwilczynski@...nel.org>, 
	Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>, linux-pci@...r.kernel.org, 
	linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org, mayank.rana@....qualcomm.com, 
	quic_vbadigan@...cinc.com
Subject: Re: [PATCH] PCI: qcom: Program correct T_POWER_ON value for L1.2
 exit timing

On Thu, Nov 06, 2025 at 10:30:44AM +0530, Krishna Chaitanya Chundru wrote:
> 
> On 11/4/2025 11:26 PM, Bjorn Helgaas wrote:
> > On Tue, Nov 04, 2025 at 05:42:45PM +0530, Krishna Chaitanya Chundru wrote:
> > > The T_POWER_ON indicates the time (in μs) that a Port requires the port
> > > on the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ#
> > > asserted before actively driving the interface. This value is used by
> > > the ASPM driver to compute the LTR_L1.2_THRESHOLD.
> > > 
> > > Currently, the root port exposes a T_POWER_ON value of zero in the L1SS
> > > capability registers, leading to incorrect LTR_L1.2_THRESHOLD calculations.
> > > This can result in improper L1.2 exit behavior and can trigger AER's.
> > > 
> > > To address this, program the T_POWER_ON value to 80us (scale = 1,
> > > value = 8) in the PCI_L1SS_CAP register during host initialization. This
> > > ensures that ASPM can take the root port's T_POWER_ON value into account
> > > while calculating the LTR_L1.2_THRESHOLD value.
> > I think the question is whether the value depends on the circuit
> > design of a particular platform (and should therefore come from DT),
> > or whether it depends solely on the qcom device.
> Yes it depends on design.
> > PCIe r7.0, sec 5.5.4, says:
> > 
> >    The T_POWER_ON and Common_Mode_Restore_Time fields must be
> >    programmed to the appropriate values based on the components and AC
> >    coupling capacitors used in the connection linking the two
> >    components. The determination of these values is design
> >    implementation specific.
> > 
> > That suggests to me that maybe there should be devicetree properties
> > related to these.  Obviously these would not be qcom-specific since
> > this is standard PCIe stuff.
> 
> Yes Bjorn these are PCIe stuff only, I can go to Device tree route if we
> have different values for each target, as of now we are using this same
> value in all targets as recommended by our HW team. If there is at least one
> more target or one more vendor who needs to program this we can take
> devicetree property route.
> 
> I am ok to go with devicetree way also if you insists. - Krishna Chaitanya.
> 

Since this is a PCI generic value, using devicetree property makes sense to me.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ