linux-kernel - Re: [PATCH v6 2/5] dt-bindings: clock, reset: Add support for rv1126b

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Message-ID: <3be7a6e4-4025-42b4-a73f-a9d05e64191d@kwiboo.se>
Date: Fri, 7 Nov 2025 15:31:02 +0100
From: Jonas Karlman <jonas@...boo.se>
To: Elaine Zhang <zhangqing@...k-chips.com>
Cc: mturquette@...libre.com, sboyd@...nel.org, sugar.zhang@...k-chips.com,
 heiko@...ech.de, robh@...nel.org, krzysztof.kozlowski+dt@...aro.org,
 conor+dt@...nel.org, devicetree@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-clk@...r.kernel.org,
 linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
 huangtao@...k-chips.com, finley.xiao@...k-chips.com,
 Conor Dooley <conor.dooley@...rochip.com>
Subject: Re: [PATCH v6 2/5] dt-bindings: clock, reset: Add support for rv1126b

Hi Elaine,

On 11/4/2025 4:06 AM, Elaine Zhang wrote:
> Add clock and reset ID defines for rv1126b.
> Also add documentation for the rv1126b CRU core.
> 
> Signed-off-by: Elaine Zhang <zhangqing@...k-chips.com>
> Acked-by: Conor Dooley <conor.dooley@...rochip.com>
> ---
>  .../bindings/clock/rockchip,rv1126b-cru.yaml  |  52 +++
>  .../dt-bindings/clock/rockchip,rv1126b-cru.h  | 392 +++++++++++++++++
>  .../dt-bindings/reset/rockchip,rv1126b-cru.h  | 405 ++++++++++++++++++
>  3 files changed, 849 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml
>  create mode 100644 include/dt-bindings/clock/rockchip,rv1126b-cru.h
>  create mode 100644 include/dt-bindings/reset/rockchip,rv1126b-cru.h

[snip]

> diff --git a/include/dt-bindings/clock/rockchip,rv1126b-cru.h b/include/dt-bindings/clock/rockchip,rv1126b-cru.h
> new file mode 100644
> index 000000000000..d6040058c21f
> --- /dev/null
> +++ b/include/dt-bindings/clock/rockchip,rv1126b-cru.h
> @@ -0,0 +1,392 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> +/*
> + * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
> + * Author: Elaine Zhang <zhangqing@...k-chips.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H
> +#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H
> +
> +/* pll clocks */
> +#define PLL_GPLL				1

The clock indices should typically start at 0 not 1.

[snip]

> +#define HCLK_RKRNG_NS				362
> +#define HCLK_RKRNG_S_NS				363
> +#define CLK_AISP_PLL_SRC			364
> +
> +/* secure clks */
> +#define CLK_USER_OTPC_S				400

And the indices should typically not contain any jumps in numbers.

Regards,
Jonas

> +#define CLK_SBPI_OTPC_S				401
> +#define PCLK_OTPC_S				402
> +#define PCLK_KEY_READER_S			403
> +#define HCLK_KL_RKCE_S				404
> +#define HCLK_RKCE_S				405
> +#define PCLK_WDT_S				406
> +#define TCLK_WDT_S				407
> +#define CLK_STIMER0				408
> +#define CLK_STIMER1				409
> +#define PLK_STIMER				410
> +#define HCLK_RKRNG_S				411
> +#define CLK_PKA_RKCE_S				412
> +#define ACLK_RKCE_S				413
> +
> +#endif

[snip]