linux-kernel - RE: [PATCH v2 1/2] iommu/amd: Add IOMMU_PROT

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Message-ID:
 <SI2PR01MB4393AF84C998C403CDCAC55CDCC3A@SI2PR01MB4393.apcprd01.prod.exchangelabs.com>
Date: Fri, 7 Nov 2025 02:39:37 +0000
From: Wei Wang <wei.w.wang@...mail.com>
To: Jason Gunthorpe <jgg@...dia.com>
CC: "alex@...zbot.org" <alex@...zbot.org>, "suravee.suthikulpanit@....com"
	<suravee.suthikulpanit@....com>, "thomas.lendacky@....com"
	<thomas.lendacky@....com>, "joro@...tes.org" <joro@...tes.org>,
	"kevin.tian@...el.com" <kevin.tian@...el.com>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "iommu@...ts.linux.dev"
	<iommu@...ts.linux.dev>
Subject: RE: [PATCH v2 1/2] iommu/amd: Add IOMMU_PROT_IE flag for memory
 encryption

On Friday, November 7, 2025 9:02 AM, Jason Gunthorpe wrote:
> On Mon, Nov 03, 2025 at 10:00:33PM +0800, Wei Wang wrote:
> > Introduce the IOMMU_PROT_IE flag to allow callers of
> > iommu_v1_map_pages() to explicitly request memory encryption for
> specific mappings.
> >
> > With SME enabled, the C-bit (encryption bit) in IOMMU page table
> > entries is now set only when IOMMU_PROT_IE is specified. This provides
> > fine-grained control over which IOVAs are encrypted through the IOMMU
> > page tables.
> >
> > Current PCIe devices and switches do not interpret the C-bit, so
> > applying it to MMIO mappings would break PCIe peer‑to‑peer
> > communication. Update the implementation to restrict C-bit usage to
> non‑MMIO backed IOVAs.
> >
> > Fixes: 2543a786aa25 ("iommu/amd: Allow the AMD IOMMU to work with
> > memory encryption")
> > Suggested-by: Jason Gunthorpe <jgg@...dia.com>
> > Signed-off-by: Wei Wang <wei.w.wang@...mail.com>
> > ---
> >  drivers/iommu/amd/amd_iommu_types.h | 3 ++-
> >  drivers/iommu/amd/io_pgtable.c      | 7 +++++--
> >  drivers/iommu/amd/iommu.c           | 2 ++
> >  3 files changed, 9 insertions(+), 3 deletions(-)
> 
> Since Joerg took the iommupt patches this will need to be rebased on his
> tree, I think it will be simpler..

OK, I will have a check, thanks.