linux-kernel - Re: [PATCH v4 2/4] dt-bindings: phy: Add documentation for Airoha AN7581 USB PHY

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20251107-marina-cramp-cf3d60a52524@spud>
Date: Fri, 7 Nov 2025 18:13:18 +0000
From: Conor Dooley <conor@...nel.org>
To: Christian Marangi <ansuelsmth@...il.com>
Cc: Vinod Koul <vkoul@...nel.org>,
	Kishon Vijay Abraham I <kishon@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Lorenzo Bianconi <lorenzo@...nel.org>,
	linux-arm-kernel@...ts.infradead.org, linux-phy@...ts.infradead.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 2/4] dt-bindings: phy: Add documentation for Airoha
 AN7581 USB PHY

On Fri, Nov 07, 2025 at 05:02:44PM +0100, Christian Marangi wrote:
> Add documentation for Airoha AN7581 USB PHY that describe the USB PHY
> for the USB controller.
> 
> Airoha AN7581 SoC support a maximum of 2 USB port. The USB 2.0 mode is
> always supported. The USB 3.0 mode is optional and depends on the Serdes
> mode currently configured on the system for the relevant USB port.
> 
> To correctly calibrate, the USB 2.0 port require correct value in
> "airoha,usb2-monitor-clk-sel" property. Both the 2 USB 2.0 port permit
> selecting one of the 4 monitor clock for calibration (internal clock not
> exposed to the system) but each port have only one of the 4 actually
> connected in HW hence the correct value needs to be specified in DT
> based on board and the physical port. Normally it's monitor clock 1 for
> USB1 and monitor clock 2 for USB2.
> 
> To correctly setup the Serdes mode attached to the USB 3.0 mode, the
> "airoha,usb3-serdes" property is required. This can be either
> AIROHA_SCU_SERDES_USB1 or AIROHA_SCU_SERDES_USB2 and is used to identify
> what modes support the PHY and what register to use to setup the
> requested mode.
> 
> The first USB port on the SoC can be both used for USB 3.0 operation or
> Ethernet (HSGMII).
> The second USB port on the SoC can be both used for USB 3.0 operation or
> for an additional PCIe line.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@...il.com>

Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>

Thanks for the updates.

Download attachment "signature.asc" of type "application/pgp-signature" (229 bytes)