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Message-ID: <abf79d96-72c2-453b-aa2d-0626be584baa@oss.qualcomm.com>
Date: Fri, 7 Nov 2025 09:58:48 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Akhil P Oommen <akhilpo@....qualcomm.com>,
Rob Clark <robin.clark@....qualcomm.com>, Sean Paul <sean@...rly.run>,
Konrad Dybcio <konradybcio@...nel.org>,
Dmitry Baryshkov <lumag@...nel.org>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Jessica Zhang <jesszhan0024@...il.com>
Cc: Dan Carpenter <dan.carpenter@...aro.org>, linux-arm-msm@...r.kernel.org,
dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
Jie Zhang <quic_jiezh@...cinc.com>
Subject: Re: [PATCH v2 1/6] drm/msm/a6xx: Add support for Adreno 612
On 11/6/25 9:50 PM, Akhil P Oommen wrote:
> From: Jie Zhang <quic_jiezh@...cinc.com>
>
> Add support for Adreno 612 GPU found in SM6150/QCS615 chipsets.
> A612 falls under ADRENO_6XX_GEN1 family and is a cut down version
> of A615 GPU.
>
> A612 has a new IP called Reduced Graphics Management Unit or RGMU
> which is a small state machine which helps to toggle GX GDSC
> (connected to CX rail) to implement IFPC feature. It doesn't support
> any other features of a full fledged GMU like clock control, resource
> voting to rpmh etc. So we need linux clock driver support like other
> gmu-wrapper implementations to control gpu core clock and gpu GX gdsc.
> This patch skips RGMU core initialization and act more like a
> gmu-wrapper case.
>
> Signed-off-by: Jie Zhang <quic_jiezh@...cinc.com>
> Signed-off-by: Akhil P Oommen <akhilpo@....qualcomm.com>
> ---
[...]
> /* Enable fault detection */
> - if (adreno_is_a730(adreno_gpu) ||
> + if (adreno_is_a612(adreno_gpu) ||
> + adreno_is_a730(adreno_gpu) ||
> adreno_is_a740_family(adreno_gpu))
> gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfffff);
Downstream sets this to 0x3fffff, but IDK if having a timeout too
large is an issue
Konrad
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