linux-kernel - Re: [PATCH v3 03/21] clk: mediatek: fix mfg mux issue

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Message-ID: <5faabbd0-2e7b-46ec-8da0-7be24f2e888e@collabora.com>
Date: Fri, 7 Nov 2025 10:34:12 +0100
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: "irving.ch.lin" <irving-ch.lin@...iatek.com>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd
 <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Matthias Brugger <matthias.bgg@...il.com>,
 Ulf Hansson <ulf.hansson@...aro.org>,
 Richard Cochran <richardcochran@...il.com>
Cc: Qiqi Wang <qiqi.wang@...iatek.com>, linux-clk@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-mediatek@...ts.infradead.org,
 linux-pm@...r.kernel.org, netdev@...r.kernel.org,
 Project_Global_Chrome_Upstream_Group@...iatek.com, sirius.wang@...iatek.com,
 vince-wl.liu@...iatek.com, jh.hsu@...iatek.com
Subject: Re: [PATCH v3 03/21] clk: mediatek: fix mfg mux issue

Il 06/11/25 13:41, irving.ch.lin ha scritto:
> From: Irving-CH Lin <irving-ch.lin@...iatek.com>
> 
> MFG mux design is different for MTK SoCs,
> For MT8189, we need to enable parent first
> to garentee parent clock stable.
> 

Title:
clk: mediatek: clk-mux: Make sure bypass clk enabled while setting MFG rate

Also, please add a Fixes tag, this is not only useful for MT8189 - for the
others, this worked because the bypass (alt) clock is already enabled due to
it being a MFG power domain requirement, but the parent still needs to be enabled
otherwise there's no input clock to MFG during the PLL reconfiguration.

Besides, please clarify the commit description (and no, 8189 is not special
and doesn't really have a mux design that is all that different from the others).

> Signed-off-by: Irving-CH Lin <irving-ch.lin@...iatek.com>
> ---
>   drivers/clk/mediatek/clk-mux.c | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c
> index c5af6dc078a3..15309c7dbbfb 100644
> --- a/drivers/clk/mediatek/clk-mux.c
> +++ b/drivers/clk/mediatek/clk-mux.c
> @@ -414,16 +414,20 @@ static int mtk_clk_mux_notifier_cb(struct notifier_block *nb,
>   	struct clk_notifier_data *data = _data;
>   	struct clk_hw *hw = __clk_get_hw(data->clk);
>   	struct mtk_mux_nb *mux_nb = to_mtk_mux_nb(nb);
> +	struct clk_hw *p_hw = clk_hw_get_parent_by_index(hw,
> +							 mux_nb->bypass_index);

Fits in one line, 84 columns is ok.

>   	int ret = 0;
>   
>   	switch (event) {
>   	case PRE_RATE_CHANGE:
> +		clk_prepare_enable(p_hw->clk);

You have to check for error here - if you can't enable the clock, your system
is going to crash as soon as you switch parents.

Cheers,
Angelo

>   		mux_nb->original_index = mux_nb->ops->get_parent(hw);
>   		ret = mux_nb->ops->set_parent(hw, mux_nb->bypass_index);
>   		break;
>   	case POST_RATE_CHANGE:
>   	case ABORT_RATE_CHANGE:
>   		ret = mux_nb->ops->set_parent(hw, mux_nb->original_index);
> +		clk_disable_unprepare(p_hw->clk);
>   		break;
>   	}
>