linux-kernel - Re: Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu

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Message-Id: <43109A90-8447-4006-8E29-2D2C0866758F@iscas.ac.cn>
Date: Sat, 8 Nov 2025 21:59:06 +0800
From: revy <gaohan@...as.ac.cn>
To: Krzysztof Kozlowski <krzk@...nel.org>
Cc: Paul Walmsley <pjw@...nel.org>,
 Palmer Dabbelt <palmer@...belt.com>,
 Albert Ou <aou@...s.berkeley.edu>,
 Alexandre Ghiti <alex@...ti.fr>,
 Rob Herring <robh@...nel.org>,
 krzk+dt@...nel.org,
 conor+dt@...nel.org,
 Chen-Yu Tsai <wens@...e.org>,
 Jernej Skrabec <jernej.skrabec@...il.com>,
 Samuel Holland <samuel@...lland.org>,
 Yixun Lan <dlan@...too.org>,
 Drew Fustini <fustini@...nel.org>,
 geert+renesas@...der.be,
 Guodong Xu <guodong@...cstar.com>,
 Haylen Chu <heylenay@....org>,
 Joel Stanley <joel@....id.au>,
 linux-riscv@...ts.infradead.org,
 linux-kernel@...r.kernel.org,
 devicetree@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org,
 linux-sunxi@...ts.linux.dev,
 Han Gao <rabenda.cn@...il.com>
Subject: Re: Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu




> -----Original Messages-----
> From: "Krzysztof Kozlowski" <krzk@...nel.org>
> Sent Time: 2025-11-08 19:29:07 (Saturday)
> To: gaohan@...as.ac.cn, "Paul Walmsley" <pjw@...nel.org>, "Palmer Dabbelt" <palmer@...belt.com>, "Albert Ou" <aou@...s.berkeley.edu>, "Alexandre Ghiti" <alex@...ti.fr>, "Rob Herring" <robh@...nel.org>, "Krzysztof Kozlowski" <krzk+dt@...nel.org>, "Conor Dooley" <conor+dt@...nel.org>, "Chen-Yu Tsai" <wens@...e.org>, "Jernej Skrabec" <jernej.skrabec@...il.com>, "Samuel Holland" <samuel@...lland.org>, "Yixun Lan" <dlan@...too.org>, "Drew Fustini" <fustini@...nel.org>, "Geert Uytterhoeven" <geert+renesas@...der.be>, "Guodong Xu" <guodong@...cstar.com>, "Haylen Chu" <heylenay@....org>, "Joel Stanley" <joel@....id.au>
> Cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-sunxi@...ts.linux.dev, "Han Gao" <rabenda.cn@...il.com>
> Subject: Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu
> 
> On 08/11/2025 09:20, gaohan@...as.ac.cn wrote:
>> From: Han Gao <gaohan@...as.ac.cn>
>> 
>> Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V,
>> using different IPs.
>> 
>> d1(s): Xuantie C906
>> v821: Andes A27 + XuanTie E907
>> v861/v881: XuanTie C907
>> 
>> Signed-off-by: Han Gao <gaohan@...as.ac.cn>
>> ---
>> arch/riscv/Kconfig.socs | 22 +++++++++++++++++-----
>> 1 file changed, 17 insertions(+), 5 deletions(-)
>> 
>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
>> index 848e7149e443..7cba5d6ec4c3 100644
>> --- a/arch/riscv/Kconfig.socs
>> +++ b/arch/riscv/Kconfig.socs
>> @@ -54,14 +54,26 @@ config SOC_STARFIVE
>> 	help
>> 	  This enables support for StarFive SoC platform hardware.
>> 
>> -config ARCH_SUNXI
>> -	bool "Allwinner sun20i SoCs"
>> +menuconfig ARCH_SUNXI
>> +	bool "Allwinner RISC-V SoCs"
>> +
>> +if ARCH_SUNXI
>> +
>> +config ARCH_SUNXI_XUANTIE
> 
> 
> You should not get multiple ARCHs. ARCH is only one. There is also not
> much rationale in commit msg for that.

The main goal is to avoid choosing multiple IP addresses for erreta. 
If using Andes IPs, I don't want to choose XuanTIe (T-Head) ERRETA.

For example, v821 uses Andes ax27, but it used to select ERRATA_THEAD.

> 
> Best regards,
> Krzysztof