linux-kernel - Re: [PATCH v3 2/4] clk: amlogic: Improve the issue of PLL lock failures

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Message-ID: <CAFBinCDbx96byeCvLY-Cq2d7r4+RipUVuER57mz1zZ4fgqRd4A@mail.gmail.com>
Date: Sat, 8 Nov 2025 22:04:19 +0100
From: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To: chuan.liu@...ogic.com
Cc: Neil Armstrong <neil.armstrong@...aro.org>, Jerome Brunet <jbrunet@...libre.com>, 
	Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	Kevin Hilman <khilman@...libre.com>, linux-amlogic@...ts.infradead.org, 
	linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 2/4] clk: amlogic: Improve the issue of PLL lock failures

On Fri, Oct 31, 2025 at 9:10 AM Chuan Liu via B4 Relay
<devnull+chuan.liu.amlogic.com@...nel.org> wrote:
>
> From: Chuan Liu <chuan.liu@...ogic.com>
>
> Due to factors such as temperature and process variations, the
> internal circuits of the PLL may require a longer time to reach a
> steady state, which can result in occasional lock failures on some
> SoCs under low-temperature conditions.
>
> After enabling the PLL and releasing its reset, a 20 us delay is
> added at each step to provide enough time for the internal PLL
> circuit to stabilize, thus reducing the probability of PLL lock
> failure.
>
> Signed-off-by: Chuan Liu <chuan.liu@...ogic.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com> # Odroid-C1