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Message-ID: <20251109185717.GBaRDkDUVYCHa_M7aP@fat_crate.local>
Date: Sun, 9 Nov 2025 19:57:17 +0100
From: Borislav Petkov <bp@...en8.de>
To: niravkumarlaxmidas.rabara@...era.com
Cc: dinguyen@...nel.org, tony.luck@...el.com, linux-edac@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] EDAC/altera: Handle OCRAM ECC enable after warm reset
On Mon, Nov 03, 2025 at 10:09:20PM +0800, niravkumarlaxmidas.rabara@...era.com wrote:
> From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@...era.com>
>
> The OCRAM ECC is always enabled either by the BootROM or by the Secure
> Device Manager (SDM) during a power-on reset on SoCFPGA.
>
> However, during a warm reset, the OCRAM content is retained to preserve
> data, while the control and status registers are reset to their default
> values. As a result, ECC must be explicitly re-enabled after a warm reset.
>
> Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@...era.com>
> ---
> drivers/edac/altera_edac.c | 18 +++++++++++++++---
> 1 file changed, 15 insertions(+), 3 deletions(-)
Does this need to go stable?
Fixes: tag?
--
Regards/Gruss,
Boris.
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