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Message-Id: <20251110-nor-v1-1-cde50c81db05@nxp.com>
Date: Mon, 10 Nov 2025 12:02:56 +0800
From: Haibo Chen <haibo.chen@....com>
To: Tudor Ambarus <tudor.ambarus@...aro.org>,
Pratyush Yadav <pratyush@...nel.org>, Michael Walle <mwalle@...nel.org>,
Miquel Raynal <miquel.raynal@...tlin.com>,
Richard Weinberger <richard@....at>, Vignesh Raghavendra <vigneshr@...com>
Cc: linux-mtd@...ts.infradead.org, linux-kernel@...r.kernel.org,
Haibo Chen <haibo.chen@....com>, imx@...ts.linux.dev
Subject: [PATCH 1/4] mtd: spi-nor: micron-st: rename the die_late_init
functions
st_nor_two/four_die_late_init() also suit for micron chips, so
rename to micron_st_nor_two/four_die_late_init().
Signed-off-by: Haibo Chen <haibo.chen@....com>
---
drivers/mtd/spi-nor/micron-st.c | 70 ++++++++++++++++++++---------------------
1 file changed, 35 insertions(+), 35 deletions(-)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 187239ccd549510c6e9a6eacf4ae41158287e077..92eb14ca76c57f29ece1edb3fe652c56d1c2888f 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -127,6 +127,38 @@ static int micron_st_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
micron_st_nor_octal_dtr_dis(nor);
}
+static int micron_st_nor_four_die_late_init(struct spi_nor *nor)
+{
+ struct spi_nor_flash_parameter *params = nor->params;
+
+ params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
+ params->n_dice = 4;
+
+ /*
+ * Unfortunately the die erase opcode does not have a 4-byte opcode
+ * correspondent for these flashes. The SFDP 4BAIT table fails to
+ * consider the die erase too. We're forced to enter in the 4 byte
+ * address mode in order to benefit of the die erase.
+ */
+ return spi_nor_set_4byte_addr_mode(nor, true);
+}
+
+static int micron_st_nor_two_die_late_init(struct spi_nor *nor)
+{
+ struct spi_nor_flash_parameter *params = nor->params;
+
+ params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
+ params->n_dice = 2;
+
+ /*
+ * Unfortunately the die erase opcode does not have a 4-byte opcode
+ * correspondent for these flashes. The SFDP 4BAIT table fails to
+ * consider the die erase too. We're forced to enter in the 4 byte
+ * address mode in order to benefit of the die erase.
+ */
+ return spi_nor_set_4byte_addr_mode(nor, true);
+}
+
static void mt35xu512aba_default_init(struct spi_nor *nor)
{
nor->params->set_octal_dtr = micron_st_nor_set_octal_dtr;
@@ -193,48 +225,16 @@ static const struct spi_nor_fixups mt25qu512a_fixups = {
.post_bfpt = mt25qu512a_post_bfpt_fixup,
};
-static int st_nor_four_die_late_init(struct spi_nor *nor)
-{
- struct spi_nor_flash_parameter *params = nor->params;
-
- params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
- params->n_dice = 4;
-
- /*
- * Unfortunately the die erase opcode does not have a 4-byte opcode
- * correspondent for these flashes. The SFDP 4BAIT table fails to
- * consider the die erase too. We're forced to enter in the 4 byte
- * address mode in order to benefit of the die erase.
- */
- return spi_nor_set_4byte_addr_mode(nor, true);
-}
-
-static int st_nor_two_die_late_init(struct spi_nor *nor)
-{
- struct spi_nor_flash_parameter *params = nor->params;
-
- params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
- params->n_dice = 2;
-
- /*
- * Unfortunately the die erase opcode does not have a 4-byte opcode
- * correspondent for these flashes. The SFDP 4BAIT table fails to
- * consider the die erase too. We're forced to enter in the 4 byte
- * address mode in order to benefit of the die erase.
- */
- return spi_nor_set_4byte_addr_mode(nor, true);
-}
-
static const struct spi_nor_fixups n25q00_fixups = {
- .late_init = st_nor_four_die_late_init,
+ .late_init = micron_st_nor_four_die_late_init,
};
static const struct spi_nor_fixups mt25q01_fixups = {
- .late_init = st_nor_two_die_late_init,
+ .late_init = micron_st_nor_two_die_late_init,
};
static const struct spi_nor_fixups mt25q02_fixups = {
- .late_init = st_nor_four_die_late_init,
+ .late_init = micron_st_nor_four_die_late_init,
};
static const struct flash_info st_nor_parts[] = {
--
2.34.1
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