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Message-ID: <87pl9qrmvo.fsf@BLaptop.bootlin.com>
Date: Mon, 10 Nov 2025 15:19:23 +0100
From: Gregory CLEMENT <gregory.clement@...tlin.com>
To: Josua Mayer <josua@...id-run.com>, Andrew Lunn <andrew@...n.ch>,
Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>, Rob Herring
<robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>
Cc: Rabeeh Khoury <rabeeh@...id-run.com>, Yazan Shhady
<yazan.shhady@...id-run.com>, Mikhail Anikin
<mikhail.anikin@...id-run.com>, Jon Nettleton <jon@...id-run.com>,
linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org, Josua Mayer
<josua@...id-run.com>
Subject: Re: [PATCH 1/2] Revert "arm64: dts: marvell: cn9132-clearfog: fix
multi-lane pci x2 and x4 ports"
Josua Mayer <josua@...id-run.com> writes:
> This reverts commit 794a066688038df46c01e177cc6faebded0acba4 because it
> misunderstood interworking between arm trusted firmware and the common
> phy driver, and does not consistently resolve the issue it was intended
> to address.
>
> Further diagnostics have revealed the root cause for the reported system
> lock-up in a race condition between pci driver probe and clock core
> disabling unused clocks.
>
> Revert the wrong change restoring driver control over all pci lanes.
> As a temporary workaround for the original issue, users can boot with
> "clk_ignore_unused".
>
> Signed-off-by: Josua Mayer <josua@...id-run.com>
Applied on mvebu/dt64
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/cn9132-clearfog.dts | 16 ++--------------
> 1 file changed, 2 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts b/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts
> index 5cf83d8ca1f59..2507896d58f9b 100644
> --- a/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts
> +++ b/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts
> @@ -413,13 +413,7 @@ fixed-link {
> /* SRDS #0,#1,#2,#3 - PCIe */
> &cp0_pcie0 {
> num-lanes = <4>;
> - /*
> - * The mvebu-comphy driver does not currently know how to pass correct
> - * lane-count to ATF while configuring the serdes lanes.
> - * Rely on bootloader configuration only.
> - *
> - * phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
> - */
> + phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
> status = "okay";
> };
>
> @@ -481,13 +475,7 @@ &cp1_eth0 {
> /* SRDS #0,#1 - PCIe */
> &cp1_pcie0 {
> num-lanes = <2>;
> - /*
> - * The mvebu-comphy driver does not currently know how to pass correct
> - * lane-count to ATF while configuring the serdes lanes.
> - * Rely on bootloader configuration only.
> - *
> - * phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
> - */
> + phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
> status = "okay";
> };
>
>
> --
> 2.51.0
>
--
Grégory CLEMENT, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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