linux-kernel - Re: RE: [PATCH 1/2] x86/resctrl: Add io_alloc_min_cbm

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Message-ID: <f4a043d2-9cb0-41c9-a45d-31f96fd007d5@amd.com>
Date: Mon, 10 Nov 2025 13:42:17 -0600
From: Babu Moger <bmoger@....com>
To: "Luck, Tony" <tony.luck@...el.com>, Aaron Tomlin <atomlin@...mlin.com>
Cc: "Chatre, Reinette" <reinette.chatre@...el.com>,
 "Dave.Martin@....com" <Dave.Martin@....com>,
 "james.morse@....com" <james.morse@....com>,
 "babu.moger@....com" <babu.moger@....com>,
 "tglx@...utronix.de" <tglx@...utronix.de>,
 "mingo@...hat.com" <mingo@...hat.com>, "bp@...en8.de" <bp@...en8.de>,
 "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: RE: [PATCH 1/2] x86/resctrl: Add io_alloc_min_cbm_all interface
 for CBM reset

Hi Tony,

On 11/10/25 11:50, Luck, Tony wrote:
>> Does the following option work for you?
>>
>> # echo "*=0" > /sys/fs/resctrl/info/L3/io_alloc_cbm
>>
>>
>> Here,|*| represents all domains.
>>
>>
>> This functionality was introduced when adding support for the*"mbm_event" assign mode* (see [1]).
>> [1]https://lore.kernel.org/lkml/b894ad853e6757d40da1469bf9fca4c64684df65.1757108044.git.babu.moger@amd.com/ <https://lore.kernel.org/lkml/b894ad853e6757d40da1469bf9fca4c64684df65.1757108044.git.babu.moger@amd.com/> <https://lore.kernel.org/lkml/b894ad853e6757d40da1469bf9fca4c64684df65.1757108044.git.babu.moger@amd.com/>
>> Also, this needs to be done for all the settings like L3, MBA also SMBA.
>>
>> # echo "L3:*=f" > /sys/fs/resctrl/schemata
>>
>> # echo "MB:*=128" > /sys/fs/resctrl/schemata
>>
>> I’d like to hear from Reinette and Tony if this seems like an acceptable
>> approach.
>>
>> Thanks
> Babu,
>
> It does look like a logical extension of the mbm_event assignment syntax.
>
> But might be awkward to use if the system has asymmetric domains. We don't
> currently. But if we wanted to support L2 cache allocation on hybrid platforms
> with a mix of P-core and E-core, those have historically supported different
> bit masks because the L2 caches may allow 12 bits for one core type and
> 16 for another. On such a platform:
>
> # echo "L2:*=fff" > schemata
>
> would work,. But
>
> # echo "L2:*=ffff" > schemata
>
> would try to set unimplemented bits on some cores and would fail.


I would consider this a user error, as the user is expected to know the 
supported value for the domain.
This situation can occur even now — we simply report the error and exit.

Thanks

Babu