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Message-ID: <20251110222929.2140564-5-helgaas@kernel.org>
Date: Mon, 10 Nov 2025 16:22:28 -0600
From: Bjorn Helgaas <helgaas@...nel.org>
To: linux-pci@...r.kernel.org
Cc: Christian Zigotzky <chzigotzky@...osoft.de>,
Manivannan Sadhasivam <mani@...nel.org>,
mad skateman <madskateman@...il.com>,
"R . T . Dickinson" <rtd2@...a.co.nz>,
Darren Stevens <darren@...vens-zone.net>,
John Paul Adrian Glaubitz <glaubitz@...sik.fu-berlin.de>,
Lukas Wunner <lukas@...ner.de>,
luigi burdo <intermediadc@...mail.com>,
Al <al@...azap.net>,
Roland <rol7and@....com>,
Hongxing Zhu <hongxing.zhu@....com>,
hypexed@...oo.com.au,
linuxppc-dev@...ts.ozlabs.org,
debian-powerpc@...ts.debian.org,
linux-kernel@...r.kernel.org,
Bjorn Helgaas <bhelgaas@...gle.com>
Subject: [PATCH v2 4/4] PCI/ASPM: Avoid L0s and L1 on Freescale Root Ports
From: Bjorn Helgaas <bhelgaas@...gle.com>
Christian reported that f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and
ASPM states for devicetree platforms") broke booting on the A-EON X5000.
Override the L0s and L1 Support advertised in Link Capabilities by the
X5000 Root Ports ([1957:0451]) so we don't try to enable those states.
Fixes: f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms")
Fixes: df5192d9bb0e ("PCI/ASPM: Enable only L0s and L1 for devicetree platforms")
Reported-by: Christian Zigotzky <chzigotzky@...osoft.de>
Link: https://lore.kernel.org/r/db5c95a1-cf3e-46f9-8045-a1b04908051a@xenosoft.de
Signed-off-by: Bjorn Helgaas <bhelgaas@...gle.com>
---
drivers/pci/quirks.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 922c77c627a1..b94264cd3833 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2523,6 +2523,7 @@ static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
* disable both L0s and L1 for now to be safe.
*/
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s_l1);
/*
* Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
--
2.43.0
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