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Message-Id: <20251110063801.641866-1-sarthak.garg@oss.qualcomm.com>
Date: Mon, 10 Nov 2025 12:08:01 +0530
From: Sarthak Garg <sarthak.garg@....qualcomm.com>
To: Adrian Hunter <adrian.hunter@...el.com>,
Ulf Hansson <ulf.hansson@...aro.org>
Cc: linux-mmc@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org, quic_nguyenb@...cinc.com,
quic_rampraka@...cinc.com, quic_pragalla@...cinc.com,
quic_sayalil@...cinc.com, quic_nitirawa@...cinc.com,
quic_bhaskarv@...cinc.com, kernel@....qualcomm.com,
Sarthak Garg <sarthak.garg@....qualcomm.com>
Subject: [PATCH V1] mmc: sdhci-msm: Avoid early clock doubling during HS400 transition
According to the hardware programming guide, the clock frequency must
remain below 52MHz during the transition to HS400 mode.
However,in the current implementation, the timing is set to HS400 (a
DDR mode) before adjusting the clock. This causes the clock to double
prematurely to 104MHz during the transition phase, violating the
specification and potentially resulting in CRC errors or CMD timeouts.
This change ensures that clock doubling is avoided during intermediate
transitions and is applied only when the card requires a 200MHz clock
for HS400 operation.
Signed-off-by: Sarthak Garg <sarthak.garg@....qualcomm.com>
---
drivers/mmc/host/sdhci-msm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 4e5edbf2fc9b..eca6a09a4547 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -355,7 +355,8 @@ static unsigned int msm_get_clock_mult_for_bus_mode(struct sdhci_host *host)
*/
if (ios.timing == MMC_TIMING_UHS_DDR50 ||
ios.timing == MMC_TIMING_MMC_DDR52 ||
- ios.timing == MMC_TIMING_MMC_HS400 ||
+ (ios.timing == MMC_TIMING_MMC_HS400 &&
+ ios.clock == MMC_HS200_MAX_DTR) ||
host->flags & SDHCI_HS400_TUNING)
return 2;
return 1;
--
2.34.1
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