linux-kernel - Re: [PATCH v2 3/6] dt-bindings: display/msm/rgmu: Document A612 RGMU

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Message-ID: <20251110-persimmon-wombat-of-holiness-6b3f9c@kuoka>
Date: Mon, 10 Nov 2025 08:51:31 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Akhil P Oommen <akhilpo@....qualcomm.com>
Cc: Rob Clark <robin.clark@....qualcomm.com>, Sean Paul <sean@...rly.run>, 
	Konrad Dybcio <konradybcio@...nel.org>, Dmitry Baryshkov <lumag@...nel.org>, 
	Abhinav Kumar <abhinav.kumar@...ux.dev>, Marijn Suijten <marijn.suijten@...ainline.org>, 
	David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>, 
	Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>, 
	Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Bjorn Andersson <andersson@...nel.org>, Jessica Zhang <jesszhan0024@...il.com>, 
	Dan Carpenter <dan.carpenter@...aro.org>, linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org, 
	freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, 
	Jie Zhang <jie.zhang@....qualcomm.com>
Subject: Re: [PATCH v2 3/6] dt-bindings: display/msm/rgmu: Document A612 RGMU

On Fri, Nov 07, 2025 at 02:20:08AM +0530, Akhil P Oommen wrote:
> From: Jie Zhang <jie.zhang@....qualcomm.com>
> 
> RGMU a.k.a Reduced Graphics Management Unit is a small state machine
> with the sole purpose of providing IFPC (Inter Frame Power Collapse)
> support. Compared to GMU, it doesn't manage GPU clock, voltage
> scaling, bw voting or any other functionalities. All it does is detect
> an idle GPU and toggle the GDSC switch. As it doesn't access DDR space,
> it doesn't require iommu.
> 
> So far, only Adreno 612 GPU has an RGMU core. Document RGMU in the GMU's
> schema.
> 
> Signed-off-by: Jie Zhang <jie.zhang@....qualcomm.com>
> Signed-off-by: Akhil P Oommen <akhilpo@....qualcomm.com>
> ---
>  .../devicetree/bindings/display/msm/rgmu.yaml      | 131 +++++++++++++++++++++
>  MAINTAINERS                                        |   1 +
>  2 files changed, 132 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/msm/rgmu.yaml b/Documentation/devicetree/bindings/display/msm/rgmu.yaml
> new file mode 100644
> index 000000000000..7621556477d0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/rgmu.yaml

Filename matching compatible, so qcom,adreno-rgmu.yaml


> @@ -0,0 +1,131 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> +%YAML 1.2
> +---
> +
> +$id: http://devicetree.org/schemas/display/msm/rgmu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RGMU attached to certain Adreno GPUs
> +
> +maintainers:
> +  - Rob Clark <robin.clark@....qualcomm.com>
> +
> +description: |

Do not need '|' unless you need to preserve formatting.

> +  RGMU (Reduced Graphics Management Unit) IP is present in some GPUs that
> +  belong to Adreno A6xx family. It is a small state machine that helps to
> +  toggle the GX GDSC (connected to CX rail) to implement IFPC feature and save
> +  power.
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: qcom,adreno-rgmu-612.0
> +      - const: qcom,adreno-rgmu
> +
> +  reg:
> +    items:
> +      - description: Core RGMU registers
> +
> +  reg-names:
> +    items:
> +      - const: gmu

Drop reg-names, useless for one entry with same name as the block name.

> +
> +  clocks:
> +    items:
> +      - description: GMU clock
> +      - description: GPU CX clock
> +      - description: GPU AXI clock
> +      - description: GPU MEMNOC clock
> +      - description: GPU SMMU vote clock
> +
> +  clock-names:
> +    items:
> +      - const: gmu
> +      - const: cxo
> +      - const: axi
> +      - const: memnoc
> +      - const: smmu_vote
> +
> +  power-domains:
> +    items:
> +      - description: CX GDSC power domain
> +      - description: GX GDSC power domain
> +
> +  power-domain-names:
> +    items:
> +      - const: cx
> +      - const: gx
> +
> +  interrupts:
> +    items:
> +      - description: GMU OOB interrupt
> +      - description: GMU interrupt
> +
> +  interrupt-names:
> +    items:
> +      - const: oob
> +      - const: gmu
> +
> +  operating-points-v2: true
> +  opp-table:
> +    type: object
> +
> +required:

compatible

> +  - reg
> +  - reg-names
> +  - clocks
> +  - clock-names
> +  - power-domains
> +  - power-domain-names
> +  - interrupts
> +  - interrupt-names

Keep the same order as in properties.

> +  - operating-points-v2
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,qcs615-gpucc.h>
> +    #include <dt-bindings/clock/qcom,qcs615-gcc.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/power/qcom,rpmhpd.h>
> +
> +    rgmu: rgmu@...a000 {

Drop label.

Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
If you cannot find a name matching your device, please check in kernel
sources for similar cases or you can grow the spec (via pull request to
DT spec repo).

Best regards,
Krzysztof