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Message-ID: <20251110090900.1412-1-zhangsenchuan@eswincomputing.com>
Date: Mon, 10 Nov 2025 17:08:59 +0800
From: zhangsenchuan@...incomputing.com
To: bhelgaas@...gle.com,
mani@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
lpieralisi@...nel.org,
kwilczynski@...nel.org,
robh@...nel.org,
p.zabel@...gutronix.de,
jingoohan1@...il.com,
gustavo.pimentel@...opsys.com,
linux-pci@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
christian.bruel@...s.st.com,
mayank.rana@....qualcomm.com,
shradha.t@...sung.com,
krishna.chundru@....qualcomm.com,
thippeswamy.havalige@....com,
inochiama@...il.com
Cc: ningyu@...incomputing.com,
linmin@...incomputing.com,
pinkesh.vaghela@...fochips.com,
ouyanghui@...incomputing.com,
Senchuan Zhang <zhangsenchuan@...incomputing.com>
Subject: [PATCH v5 1/2] dt-bindings: PCI: eic7700: Add Eswin PCIe host controller
From: Senchuan Zhang <zhangsenchuan@...incomputing.com>
Add Device Tree binding documentation for the Eswin EIC7700 PCIe
controller module, the PCIe controller enables the core to correctly
initialize and manage the PCIe bus and connected devices.
Signed-off-by: Yu Ning <ningyu@...incomputing.com>
Signed-off-by: Yanghui Ou <ouyanghui@...incomputing.com>
Signed-off-by: Senchuan Zhang <zhangsenchuan@...incomputing.com>
---
.../bindings/pci/eswin,eic7700-pcie.yaml | 167 ++++++++++++++++++
1 file changed, 167 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/eswin,eic7700-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/eswin,eic7700-pcie.yaml b/Documentation/devicetree/bindings/pci/eswin,eic7700-pcie.yaml
new file mode 100644
index 000000000000..9c0150834e6d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/eswin,eic7700-pcie.yaml
@@ -0,0 +1,167 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/eswin,eic7700-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Eswin EIC7700 PCIe host controller
+
+maintainers:
+ - Yu Ning <ningyu@...incomputing.com>
+ - Senchuan Zhang <zhangsenchuan@...incomputing.com>
+ - Yanghui Ou <ouyanghui@...incomputing.com>
+
+description:
+ Eswin EIC7700 SoC PCIe root complex controller is based on the Synopsys
+ DesignWare PCIe IP.
+
+properties:
+ compatible:
+ const: eswin,eic7700-pcie
+
+ reg:
+ maxItems: 3
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: config
+ - const: elbi
+
+ ranges:
+ maxItems: 3
+
+ '#interrupt-cells':
+ const: 1
+
+ interrupt-names:
+ items:
+ - const: msi
+ - const: inta
+ - const: intb
+ - const: intc
+ - const: intd
+
+ interrupt-map:
+ maxItems: 4
+
+ interrupt-map-mask:
+ items:
+ - const: 0
+ - const: 0
+ - const: 0
+ - const: 7
+
+ clocks:
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: mstr
+ - const: dbi
+ - const: phy_reg
+ - const: aux
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: dbi
+ - const: pwr
+
+patternProperties:
+ "^pcie@":
+ type: object
+ $ref: /schemas/pci/pci-pci-bridge.yaml#
+
+ properties:
+ reg:
+ maxItems: 1
+
+ num-lanes:
+ maximum: 4
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: perst
+
+ required:
+ - reg
+ - ranges
+ - num-lanes
+ - resets
+ - reset-names
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - ranges
+ - interrupts
+ - interrupt-names
+ - interrupt-map-mask
+ - interrupt-map
+ - '#interrupt-cells'
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@...00000 {
+ compatible = "eswin,eic7700-pcie";
+ reg = <0x0 0x54000000 0x0 0x4000000>,
+ <0x0 0x40000000 0x0 0x800000>,
+ <0x0 0x50000000 0x0 0x100000>;
+ reg-names = "dbi", "config", "elbi";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x01000000 0x0 0x40800000 0x0 0x40800000 0x0 0x800000>,
+ <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0xf000000>,
+ <0x43000000 0x80 0x00000000 0x80 0x00000000 0x2 0x00000000>;
+ bus-range = <0x00 0xff>;
+ clocks = <&clock 144>,
+ <&clock 145>,
+ <&clock 146>,
+ <&clock 147>;
+ clock-names = "mstr", "dbi", "phy_reg", "aux";
+ resets = <&reset 97>,
+ <&reset 98>;
+ reset-names = "dbi", "pwr";
+ interrupts = <220>, <179>, <180>, <181>, <182>, <183>, <184>, <185>, <186>;
+ interrupt-names = "msi", "inta", "intb", "intc", "intd";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 179>,
+ <0x0 0x0 0x0 0x2 &plic 180>,
+ <0x0 0x0 0x0 0x3 &plic 181>,
+ <0x0 0x0 0x0 0x4 &plic 182>;
+ device_type = "pci";
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ device_type = "pci";
+ num-lanes = <4>;
+ resets = <&reset 99>;
+ reset-names = "perst";
+ };
+ };
+ };
--
2.25.1
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