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Message-ID: <97eb5ae9-6c99-497e-a1b9-80bf365bf2d5@linux.intel.com>
Date: Mon, 10 Nov 2025 17:15:39 +0800
From: "Mi, Dapeng" <dapeng1.mi@...ux.intel.com>
To: Peter Zijlstra <peterz@...radead.org>
Cc: Ingo Molnar <mingo@...hat.com>, Arnaldo Carvalho de Melo
 <acme@...nel.org>, Namhyung Kim <namhyung@...nel.org>,
 Ian Rogers <irogers@...gle.com>, Adrian Hunter <adrian.hunter@...el.com>,
 Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
 Andi Kleen <ak@...ux.intel.com>, Eranian Stephane <eranian@...gle.com>,
 linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org,
 Dapeng Mi <dapeng1.mi@...el.com>, Zide Chen <zide.chen@...el.com>,
 Falcon Thomas <thomas.falcon@...el.com>, Xudong Hao <xudong.hao@...el.com>
Subject: Re: [Patch v9 10/12] perf/x86/intel: Update dyn_constranit base on
 PEBS event precise level


On 11/10/2025 5:03 PM, Peter Zijlstra wrote:
> On Mon, Nov 10, 2025 at 08:23:55AM +0800, Mi, Dapeng wrote:
>
>>> @@ -5536,6 +5540,14 @@ static void intel_pmu_check_dyn_constr(s
>>>  				continue;
>>>  			mask = hybrid(pmu, acr_cause_mask64) & GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0);
>>>  			break;
>>> +		case DYN_CONSTR_PEBS:
>>> +			if (x86_pmu.arch_pebs)
>>> +				mask = hybrid(pmu, arch_pebs_cap).counters;
>>> +			break;
>>> +		case DYN_CONSTR_PDIST:
>>> +			if (x86_pmu.arch_pebs)
>>> +				mask = hybrid(pmu, arch_pebs_cap).pdists;
>>> +			break;
>>>  		default:
>>>  			pr_warn("Unsupported dynamic constraint type %d\n", i);
>>>  		}
>> Yes, exactly. Thanks.
> Excellent. Could you please double check and try the bits I have in
> queue/perf/core ? I don't think I've got v6 hardware at hand.

Sure. I would post test results tomorrow.



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