linux-kernel - Re: [PATCH 4/4] usb: dwc3: add support for configurable DMA addressable bits

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Message-ID: <20251111-aardwolf-of-unmatched-potency-7a2eff@kuoka>
Date: Tue, 11 Nov 2025 09:14:55 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: adrianhoyin.ng@...era.com
Cc: gregkh@...uxfoundation.org, robh@...nel.org, krzk+dt@...nel.org, 
	conor+dt@...nel.org, dinguyen@...nel.org, Thinh.Nguyen@...opsys.com, 
	devicetree@...r.kernel.org, linux-usb@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 4/4] usb: dwc3: add support for configurable DMA
 addressable bits

On Tue, Nov 11, 2025 at 02:18:48PM +0800, adrianhoyin.ng@...era.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@...era.com>
> 
> Add support for configuring the DMA addressable bit width in the
> Synopsys DesignWare USB3 (DWC3) core driver.
> 
> Altera Agilex5 supports only 40-bit DMA addressing. Setting an incorrect
> DMA mask (such as the default 64-bit) can lead to address truncation or
> translation faults when the SMMU is enabled.
> 
> This commit introduces a new field, dma_addressable_bits, in the dwc3
> structure to track the platform’s supported DMA width. The default value
> is set to 64 bits, but for Agilex5 platforms (altr,agilex5-dwc3), the
> value is overridden to 40 bits. This field is then used when setting the
> DMA mask to ensure compatibility with the system’s actual address bus
> capabilities.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@...era.com>
> ---
>  drivers/usb/dwc3/core.c | 9 ++++++++-
>  drivers/usb/dwc3/core.h | 3 +++
>  2 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index ae140c356295..20e655364135 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -2179,6 +2179,9 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
>  	dwc->xhci_resources[0].flags = res->flags;
>  	dwc->xhci_resources[0].name = res->name;
>  
> +	/* Initialize dma addressable bit to 64 bits as default */
> +	dwc->dma_addressable_bits = 64;
> +
>  	/*
>  	 * Request memory region but exclude xHCI regs,
>  	 * since it will be requested by the xhci-plat driver.
> @@ -2194,6 +2197,9 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
>  			dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START;
>  		}
>  
> +		if (of_device_is_compatible(parent, "altr,agilex5-dwc3"))

No, this does not scale. Don't sprinkle compatible all over driver code.
You have driver match data for that.

Best regards,
Krzysztof