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Message-Id: <20251112173314.1751671-1-tmaimon77@gmail.com>
Date: Wed, 12 Nov 2025 19:33:14 +0200
From: Tomer Maimon <tmaimon77@...il.com>
To: robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
broonie@...nel.org,
avifishman70@...il.com,
tali.perry1@...il.com,
joel@....id.au,
venture@...gle.com,
yuenn@...gle.com,
benjaminfair@...gle.com,
andrew@...econstruct.com.au
Cc: openbmc@...ts.ozlabs.org,
devicetree@...r.kernel.org,
linux-spi@...r.kernel.org,
linux-kernel@...r.kernel.org,
Tomer Maimon <tmaimon77@...il.com>
Subject: [PATCH v1] spi: dt-bindings: nuvoton,npcm-fiu: Convert to DT schema
Convert the Nuvoton NPCM FIU binding to DT schema format.
Signed-off-by: Tomer Maimon <tmaimon77@...il.com>
---
.../bindings/spi/nuvoton,npcm-fiu.txt | 58 -------------
.../bindings/spi/nuvoton,npcm-fiu.yaml | 87 +++++++++++++++++++
2 files changed, 87 insertions(+), 58 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.yaml
diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
deleted file mode 100644
index fb38e96d395f..000000000000
--- a/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-* Nuvoton FLASH Interface Unit (FIU) SPI Controller
-
-NPCM FIU supports single, dual and quad communication interface.
-
-The NPCM7XX supports three FIU modules,
-FIU0 and FIUx supports two chip selects,
-FIU3 support four chip select.
-
-The NPCM8XX supports four FIU modules,
-FIU0 and FIUx supports two chip selects,
-FIU1 and FIU3 supports four chip selects.
-
-Required properties:
- - compatible : "nuvoton,npcm750-fiu" for Poleg NPCM7XX BMC
- "nuvoton,npcm845-fiu" for Arbel NPCM8XX BMC
- - #address-cells : should be 1.
- - #size-cells : should be 0.
- - reg : the first contains the register location and length,
- the second contains the memory mapping address and length
- - reg-names: Should contain the reg names "control" and "memory"
- - clocks : phandle of FIU reference clock.
-
-Required properties in case the pins can be muxed:
- - pinctrl-names : a pinctrl state named "default" must be defined.
- - pinctrl-0 : phandle referencing pin configuration of the device.
-
-Optional property:
- - nuvoton,spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.
-
-Aliases:
-- All the FIU controller nodes should be represented in the aliases node using
- the following format 'fiu{n}' where n is a unique number for the alias.
- In the NPCM7XX BMC:
- fiu0 represent fiu 0 controller
- fiu1 represent fiu 3 controller
- fiu2 represent fiu x controller
-
- In the NPCM8XX BMC:
- fiu0 represent fiu 0 controller
- fiu1 represent fiu 1 controller
- fiu2 represent fiu 3 controller
- fiu3 represent fiu x controller
-
-Example:
-fiu3: spi@...000000 {
- compatible = "nuvoton,npcm750-fiu";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;
- reg-names = "control", "memory";
- clocks = <&clk NPCM7XX_CLK_AHB>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi3_pins>;
- flash@0 {
- ...
- };
-};
-
diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.yaml b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.yaml
new file mode 100644
index 000000000000..b12676da7426
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/nuvoton,npcm-fiu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton NPCM Flash Interface Unit (FIU) SPI Controller
+
+maintainers:
+ - Tomer Maimon <tmaimon77@...il.com>
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+description: |
+ NPCM FIU supports single, dual and quad communication interface.
+
+ The NPCM7XX supports three FIU modules:
+ FIU0 and FIUx support two chip selects
+ FIU3 supports four chip selects.
+
+ The NPCM8XX supports four FIU modules:
+ FIU0 and FIUx support two chip selects
+ FIU1 and FIU3 support four chip selects.
+
+ Alias convention:
+ The '/aliases' node should define:
+ For NPCM7xx: fiu0=&fiu0; fiu1=&fiu3; fiu2=&fiux;
+ For NPCM8xx: fiu0=&fiu0; fiu1=&fiu3; fiu2=&fiux; fiu3=&fiu1;
+
+properties:
+ compatible:
+ enum:
+ - nuvoton,npcm750-fiu # Poleg NPCM7XX
+ - nuvoton,npcm845-fiu # Arbel NPCM8XX
+
+ reg:
+ minItems: 1
+ items:
+ - description: FIU registers
+ - description: Memory-mapped flash contents (optional)
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: control
+ - const: memory
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ nuvoton,spix-mode:
+ type: boolean
+ description: Enable SPIX mode for an expansion bus to an ASIC or CPLD.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
+ fiu3: spi@...00000 {
+ compatible = "nuvoton,npcm750-fiu";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfb000000 0x1000>,
+ <0x80000000 0x10000000>;
+ reg-names = "control", "memory";
+ clocks = <&clk NPCM7XX_CLK_AHB>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi3_pins>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
--
2.34.1
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